A deep sub-micron timing measurement circuit using a single-stage Vernier delay line

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) ◽

10.1109/cicc.2002.1012770 ◽

2003 ◽

Author(s):

A.H. Chan ◽

G.W. Roberts

Keyword(s):

Single Stage ◽

Measurement Circuit ◽

Timing Measurement

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Experimental verification of timing measurement circuit with self-calibration

19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings ◽

10.1109/ims3tw.2014.6997393 ◽

2014 ◽

Author(s):

Takeshi Chujo ◽

Daiki Hirabayashi ◽

Congbing Li ◽

Yutaro Kobayashi ◽

Junshan Wang ◽

...

Keyword(s):

Experimental Verification ◽

Measurement Circuit ◽

Self Calibration ◽

Timing Measurement

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A Time Interval Measurement Circuit Based on Delay Line Interpolation

Open Journal of Circuits and Systems ◽

10.12677/ojcs.2015.41002 ◽

2015 ◽

Vol 04 (01) ◽

pp. 8-14

Author(s):

炜张

Keyword(s):

Time Interval ◽

Measurement Circuit ◽

Interval Measurement ◽

Time Interval Measurement

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A 10-GHz Delay Line Frequency Discriminator and PD/CP-Based CMOS Phase Noise Measurement Circuit

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2017.2650222 ◽

2017 ◽

Vol 65 (7) ◽

pp. 2361-2372 ◽

Author(s):

Shilei Hao ◽

Tongning Hu ◽

Qun Jane Gu

Keyword(s):

Phase Noise ◽

Noise Measurement ◽

Measurement Circuit ◽

Line Frequency ◽

Frequency Discriminator

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Scheduling algorithms for shared fiber-delay-line optical packet switches - the single-stage case

IEEE Global Telecommunications Conference, 2004. GLOBECOM '04. ◽

10.1109/glocom.2004.1378309 ◽

2005 ◽

Author(s):

Soung Y. Liew ◽

Gang Hu ◽

H.J. Chao

Keyword(s):

Scheduling Algorithms ◽

Single Stage ◽

Packet Switches ◽

Fiber Delay Line

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A 10 GHz delay line frequency discriminator and PD/CP based CMOS phase noise measurement circuit with −138.6 dBc/Hz sensitivity at 1 MHz offset

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ◽

10.1109/rfic.2015.7337705 ◽

2015 ◽

Author(s):

Shilei Hao ◽

Tongning Hu ◽

Qun Jane Gu

Keyword(s):

Phase Noise ◽

Noise Measurement ◽

Measurement Circuit ◽

Line Frequency ◽

Frequency Discriminator

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Built-in jitter measurement circuit for PLL based on variable vernier delay line

IEICE Electronics Express ◽

10.1587/elex.13.20161116 ◽

2017 ◽

Vol 14 (3) ◽

pp. 20161116-20161116

Author(s):

Zhikuang Cai ◽

Haobo Xu ◽

Shanwen Hu ◽

Jun Yang

Keyword(s):

Measurement Circuit ◽

Jitter Measurement

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Scheduling algorithms for shared fiber-delay-line optical packet Switches-part I: the single-stage case

Journal of Lightwave Technology ◽

10.1109/jlt.2005.844196 ◽

2005 ◽

Vol 23 (4) ◽

pp. 1586-1600 ◽

Author(s):

S.Y. Liew ◽

Gang Hu ◽

H.J. Chao

Keyword(s):

Scheduling Algorithms ◽

Single Stage ◽

Packet Switches ◽

Fiber Delay Line

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PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00108 ◽

2019 ◽

Author(s):

Shuo Li ◽

Xiaolin Xu ◽

Wayne Burleson

Keyword(s):

Process Variations ◽

Measurement Circuit ◽

Timing Measurement

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On-chip built-in jitter measurement circuit for PLL based on duty-cycle modulation vernier delay line

Tsinghua Science & Technology ◽

10.1016/s1007-0214(07)70097-4 ◽

2007 ◽

Vol 12 (S1) ◽

pp. 128-133

Author(s):

Fei Yu ◽

Chung Len Lee ◽

Jingkai Zhang

Keyword(s):

Measurement Circuit ◽

Jitter Measurement ◽

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A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966708 ◽

2002 ◽

Author(s):

A.H. Chan ◽

G.W. Roberts

Keyword(s):

High Resolution ◽

Measurement Device ◽

Timing Measurement

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