A Time Interval Measurement Circuit Based on Delay Line Interpolation

This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.

Download Full-text

HIGH RESOLUTION TIME-INTERVAL MEASUREMENT SYSTEMS APPLIED TO FLOW MEASUREMENT

Metrology and Measurement Systems ◽

10.2478/mms-2014-0008 ◽

2014 ◽

Vol 21 (1) ◽

pp. 77-84 ◽

Cited By ~ 7

Author(s):

Sławomir Grzelak ◽

Marcin Kowalski ◽

Jarosław Czoków ◽

Marek Zieliński

Keyword(s):

High Resolution ◽

Flow Measurement ◽

Delay Line ◽

Time Interval ◽

Clock Signal ◽

Resolution Time ◽

Interval Measurement ◽

Measurement Systems ◽

Field Programmable ◽

Time Interval Measurement

Abstract The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

Download Full-text

Multi tapped delay line time-interval measurement system implemented in a programmable structure

ACTA IMEKO ◽

10.21014/acta_imeko.v3i3.57 ◽

2014 ◽

Vol 3 (3) ◽

pp. 43 ◽

Cited By ~ 1

Author(s):

Marek Zielinski ◽

Dariusz Chaberski ◽

Maciej Gurski ◽

Marcin Kowalski

Keyword(s):

Energy Consumption ◽

Measurement System ◽

Delay Line ◽

Time Interval ◽

Delay Lines ◽

Interval Measurement ◽

Time Stamps ◽

Measured Time ◽

Time Interval Measurement ◽

Total Measurement Time

This paper describes a time-interval measurement system with increased resolution using multiple taped delay lines. In this time-interval measurement system, sixteen time-stamps are registered during a single measuring cycle (one shot). It means that the value of the measured time-interval can be interpolated with higher resolution without increasing the number of measurements or the interpolation time. Limiting the total measurement time reduces the energy consumption which is particularly important in battery powered systems.

Download Full-text

UWB-IR receiver with accurate time-interval-measurement circuit for communication/location system

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5117769 ◽

2009 ◽

Cited By ~ 3

Author(s):

T. Nakagawa ◽

R. Fujiwara ◽

G. Ono ◽

M. Miyazaki

Keyword(s):

Time Interval ◽

Measurement Circuit ◽

Interval Measurement ◽

Location System ◽

Time Interval Measurement

Download Full-text

Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device

ACTA IMEKO ◽

10.21014/acta_imeko.v4i1.167 ◽

2015 ◽

Vol 4 (1) ◽

pp. 77

Author(s):

Marek Zielinski ◽

Maciej Gurski ◽

Dariusz Chaberski

Keyword(s):

High Resolution ◽

Duty Cycle ◽

Delay Line ◽

Measurement Instrument ◽

Time Interval ◽

Interval Measurement ◽

Time Stamps ◽

Measured Time ◽

Time Interval Measurement ◽

Total Measurement Time

This paper describes the architecture of a Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time-stamps during a single measuring cycle. It means that the measured time-interval can be precisely interpolated from the collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.

Download Full-text