Arbitrated IP Core Based Dynamic Task Mapping Algorithm for Networks-on-Chip

Author(s):  
Arvind Kumar ◽  
Suchi Johari ◽  
Vivek Kumar Sehgal
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.


DYNA ◽  
2014 ◽  
Vol 81 (185) ◽  
pp. 28 ◽  
Author(s):  
Freddy Bolaños-Martínez ◽  
Jose Edison Aedo ◽  
Fredy Rivera-Vélez

2015 ◽  
Vol 61 (7) ◽  
pp. 293-306 ◽  
Author(s):  
Tahir Maqsood ◽  
Sabeen Ali ◽  
Saif U.R. Malik ◽  
Sajjad A. Madani

2017 ◽  
Vol 74 ◽  
pp. 61-77 ◽  
Author(s):  
Navonil Chatterjee ◽  
Suraj Paul ◽  
Priyajit Mukherjee ◽  
Santanu Chattopadhyay

2017 ◽  
Vol 16 (4) ◽  
pp. 1-24 ◽  
Author(s):  
Navonil Chatterjee ◽  
Suraj Paul ◽  
Santanu Chattopadhyay

2016 ◽  
Vol 70 ◽  
pp. 48-58 ◽  
Author(s):  
Wei Hu ◽  
Qingsong Shi ◽  
Yonghao Wang ◽  
Kai Zhang ◽  
Jun Liu ◽  
...  

2019 ◽  
Vol 8 (2) ◽  
pp. 414-421 ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.


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