Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

System-Level Analysis of MPSoCs with a Hardware Scheduler

Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) for runtime management called OSIP on two platform paradigms: shared and distributed memory. For the former, a generic bus is used as interconnect. For distributed memory, a Network-on-Chip (NoC) is used. The effects of OSIP and the communication architecture are jointly investigated from the system point of view, based on a broad case study with real applications (an H.264 video decoder and a digital receiver for wireless communications) and a synthetic benchmark application.

Asymmetric Link Routing in Location-Aware Mobile Ad-Hoc Networks

Recent experimental research has revealed that the link conditions in realistic wireless networks vary significantly from the ideal disk model, and a substantial percentage of links are asymmetric. Many existing geographic routing protocols fail to consider asymmetric links during neighbor discovery and thus discount a significant number of potentially stable routes with good one-way reliability. This chapter provides a detailed overview of a number of location-aware routing protocols that explicitly use asymmetric links in routing to obtain efficient and shorter (low latency) routes. An asymmetric link routing protocol, called Asymmetric Geographic Forwarding (A-GF) is discussed in detail. A-GF discovers asymmetric links in the network, evaluates them for stability (e.g., based on mobility), and uses them to improve the routing efficiency.

Self-Adaptive SoCs for Dependability

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process

The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CMOS technology. Two novel types of GALS interface circuits are validated: point-to-point pausible clocking GALS interfaces and GALS NoC interconnects. Point-to-point GALS interfaces are integrated within a complex OFDM baseband transmitter block, and for NoC switches special test structures are defined. This chapter discloses the full structure of the respective interfaces, the complete GALS system, as well as the design flow utilized to implement them on the chip. Moreover, the full set of measurement results are presented, including area, power, and EMI results. Significant benefits and robustness of our applied GALS methodology are shown. Finally, some outlook and vision of the future role of GALS are outlined.

On Parallel Online Learning for Adaptive Embedded Systems

This chapter considers parallel implementation of the online multi-label regularized least-squares machine-learning algorithm for embedded hardware platforms. The authors focus on the following properties required in real-time adaptive systems: learning in online fashion, that is, the model improves with new data but does not require storing it; the method can fully utilize the computational abilities of modern embedded multi-core computer architectures; and the system efficiently learns to predict several labels simultaneously. They demonstrate on a hand-written digit recognition task that the online algorithm converges faster, with respect to the amount of training data processed, to an accurate solution than a stochastic gradient descent based baseline. Further, the authors show that our parallelization of the method scales well on a quad-core platform. Moreover, since Network-on-Chip (NoC) has been proposed as a promising candidate for future multi-core architectures, they implement a NoC system consisting of 16 cores. The proposed machine learning algorithm is evaluated in the NoC platform. Experimental results show that, by optimizing the cache behaviour of the program, cache/memory efficiency can improve significantly. Results from the chapter provide a guideline for designing future embedded multi-core machine learning devices.

Analysis of Real-Time Hybrid-Cooperative GNSS-Terrestrial Positioning Algorithms

This chapter analyzes some hybrid and cooperative GNSS-terrestrial positioning algorithms that combine both pseudorange measurements from satellites and terrestrial range measurements based on radio frequency communication to improve both positioning accuracy and availability. A Simulation Tool (ST) is also presented as a viable tool able to test and evaluate the performance of these hybrid positioning algorithms in different scenarios. In particular, the ST simulates devices belonging to a Peer-to-Peer (P2P) wireless network where peers, equipped with a wireless interface and a GNSS receiver, cooperate among them by exchanging positioning aiding data in order to enhance the overall performance. Different hybrid and cooperative algorithms, based on Bayesian and least squares approaches proposed in the literature, have been implemented in the ST and simulated in different simulation scenarios including the vehicular urban one. Moreover, all these algorithms are compared in terms of computational complexity to better understand their feasibility to achieve a real-time implementation. Finally, the sensitivity of the hybrid and cooperative algorithms when pseudorange measurements are affected by large noise and in presence of malicious peers in the P2P network is also assessed by means of the ST.

Hierarchical Agent-Based Monitoring Systems for Dynamic Reconfiguration in NoC Platforms

A Network-On-Chip is a paradigm that tackles limitations of traditional bus-based interconnects. It allows complex applications that demand many resources to be deployed on many-core platforms effectively. To satisfy requirements on dependability, however, a NoC platform requires dynamic monitoring and reconfiguration mechanisms. In this chapter, the authors propose an agent-based management system that monitors the state of the platform and applies various reconfiguration techniques. These techniques aim at enabling uninterruptable execution of applications satisfying dependability requirements. The authors develop the proposed system within Event-B that provides a means for stepwise and correct-by-construction specification supported by mathematical proofs. Furthermore, the authors show the mechanism of decomposition of Event-B specifications such that a well-structured and hierarchical agent-based management system is derived.

Model-Based Testing of Highly Configurable Embedded Systems

This chapter reports the results of a cycle computer case study and a previously conducted industrial case study from the automation domain. The key result is a model-based testing process for highly configurable embedded systems. The initial version of the testing process was built upon parameterizeable systems. The cycle computer case study adds the configuration using the product line concept and a feature model to store the parameterizable data. Thus, parameters and their constraints can be managed in a very structured way. Escalating demand for flexibility has made modern embedded software systems highly adjustable. This configurability is often realized through parameters and a highly configurable system possesses a handful of those. Small changes in parameter values can often account for significant changes in the system's behavior, whereas in some other cases, changed parameters may not result in any perceivable reaction. The case studies address the challenge of applying model-based testing to configurable embedded software systems in order to reduce development effort. As a result of the case studies, a model-based testing process was developed. This process integrates existing model-based testing methods and tools such as combinatorial design and constraint processing as well as the product line engineering approach. The testing process was applied as part of the case studies and analyzed in terms of its actual saving potentials, which turned out to reduce the testing effort by more than a third.