scholarly journals Redundant logic insertion and fault tolerance improvement in combinational circuits

2017 ◽  
Author(s):  
P. Balasubramanian ◽  
R. T. Naayagi
Keyword(s):  
Fault Tolerance ◽  
Combinational Circuits ◽  
Tolerance Improvement

Fault Tolerance Improvement for Cloud Data Center

2017 ◽  
Author(s):  
Humphrey Emesowum ◽  
◽  
Athanasios Paraskelidis ◽  
Mo Adda
Keyword(s):  
Fault Tolerance ◽  
Data Center ◽  
Cloud Data Center ◽  
Cloud Data ◽  
Tolerance Improvement

scholarly journals DEVELOPMENT OF FAIL-SAFE CONTROL SYSTEMS AGAINST HEAVY CHARGED PARTICLES OF OUTER SPACE

2021 ◽  
Author(s):  
V. Zolnikov ◽  
I. Strukov ◽  
K. Chubur ◽  
Yu. Chevychelov ◽  
A. Yankov
Keyword(s):  
Fault Tolerance ◽  
Control Systems ◽  
Outer Space ◽  
Charged Particles ◽  
Combinational Circuits ◽  
Heavy Charged Particles ◽  
Safe Control ◽  
Fail Safe

This article discusses the development of effective methods and tools for assessing the fault tolerance of logical circuits, the mechanism of logical masking, the development of the route of re-synthesis of combinational circuits, methods for increasing fault tolerance. A method of iterative circuit modification is proposed, due to an increase in the level of logical masking of the circuit.

Fault Tolerance Improvement for Cloud Data Center

2017 ◽  
pp. 412-418
Author(s):  
Humphrey Emesowum ◽  
◽  
Athanasios Paraskelidis ◽  
Mo Adda
Keyword(s):  
Fault Tolerance ◽  
Data Center ◽  
Cloud Data Center ◽  
Cloud Data ◽  
Tolerance Improvement

METHODS FOR ENSURING RESISTANCE TO HCP FOR CONTROL LOGIC AND STATIC MEMORY OF THE MICROPROCESSOR IN THE DESIGN

2020 ◽  
Vol 12 (4) ◽  
pp. 17-24
Author(s):  
Sergey Grechanyy ◽  
K. Chubur
Keyword(s):  
Fault Tolerance ◽  
Block Diagram ◽  
Charged Particles ◽  
Memory Cell ◽  
Combinational Circuits ◽  
Control Logic ◽  
Heavy Charged Particles ◽  
Critical Charge

The article describes methods for ensuring resistance to heavy charged particles (HCP) of the RAM block of the microprocessor. A description of the implementation and a block diagram of static memory based on dummy blocks is given. The paper considers methods of combating the biopolar effect, which are aimed at controlling the potential of the transistor body and reducing the resistance. The dependence of the critical charge of a SOI-memory cell the gain of a parasitic biopolar transistor is modeled. To increase the fault tolerance of combinational circuits consisting of control logic and decoder blocks, redundancy is applied at the level of individual valves.

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

2017 ◽  
Vol 25 (1) ◽  
pp. 224-237 ◽  
Author(s):  
Ahmad T. Sheikh ◽  
Aiman H. El-Maleh ◽  
Muhammad E. S. Elrabaa ◽  
Sadiq M. Sait
Keyword(s):  
Fault Tolerance ◽  
Combinational Circuits
Sign in / Sign up

Export Citation Format

Share Document