A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform

2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) ◽

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching

10.1109/cvprw.2016.110 ◽

2016 ◽

Cited By ~ 7

Author(s):

Jaco Hofmann ◽

Jens Korinth ◽

Andreas Koch

Keyword(s):

Real Time ◽

Stereo Vision ◽

High Performance ◽

Hardware Architecture ◽

Global Matching

An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis

10.1109/fpl.2009.5272490 ◽

2009 ◽

Cited By ~ 2

Author(s):

Mario Alberto Ibarra-Manzano ◽

Michel Devy ◽

Jean-Louis Boizard ◽

Pierre Lacroix ◽

Jean-Yves Fourniols

Keyword(s):

Stereo Vision ◽

Reconfigurable Architecture ◽

High Level Synthesis ◽

High Level ◽

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing ◽

10.1109/icassp.2004.1327056 ◽

2004 ◽

Author(s):

Yongtao Wang ◽

H. Mahmoodi ◽

Lih-Yih Chiou ◽

Hunsoo Choo ◽

Jongsun Park ◽

...

Keyword(s):

Low Power ◽

Adaptive Filtering ◽

High Performance ◽

Hardware Architecture ◽

Vlsi Implementation ◽

Polyphase Channelizer

A Multi-Window Stereo Vision Algorithm With Improved Performance at Object Borders

2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing ◽

10.1109/ciisp.2007.369295 ◽

2007 ◽

Author(s):

Jun Zhao ◽

Jayantha Katupitiya

Keyword(s):

Stereo Vision ◽

Improved Performance ◽

High-Performance Algorithm Adaptations and Hardware Architecture for HEVC Intra Encoders

IEEE Transactions on Circuits and Systems for Video Technology ◽

10.1109/tcsvt.2019.2913504 ◽

2019 ◽

Vol 29 (7) ◽

pp. 2138-2145 ◽

Cited By ~ 3

Author(s):

Yuanzhi Zhang ◽

Chao Lu

Keyword(s):

High Performance ◽

A high performance hardware architecture for multi-frame hierarchical motion estimation

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2011.5955224 ◽

2011 ◽

Vol 57 (2) ◽

pp. 794-801 ◽

Cited By ~ 8

Author(s):

Huong Ho ◽

Robert Klepko ◽

Nam Ninh ◽

Demin Wang

Keyword(s):

Motion Estimation ◽

High Performance ◽

A High-Performance Parallel Computation Hardware Architecture in ASIC of SHA-256 Hash

2019 21st International Conference on Advanced Communication Technology (ICACT) ◽

10.23919/icact.2019.8701906 ◽

2019 ◽

Cited By ~ 3

Author(s):

Xiaoyong Zhang ◽

Ruizhen WU ◽

Mingming Wang ◽

Lin Wang

Keyword(s):

Parallel Computation ◽

High Performance ◽

A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation

2006 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2006.313205 ◽

2006 ◽

Cited By ~ 13

Author(s):

Sinan Yalcin ◽

Ilker Hamzaoglu

Keyword(s):

Motion Estimation ◽

High Performance ◽

A Dynamic Programming Approach Based Stereo Vision Algorithm Improving Object Border Performance

2006 IEEE/RSJ International Conference on Intelligent Robots and Systems ◽

10.1109/iros.2006.282034 ◽

2006 ◽

Cited By ~ 1

Author(s):

Jun Zhao ◽

Jayantha Katupitiya

Keyword(s):

Dynamic Programming ◽

Stereo Vision ◽

Programming Approach ◽

Dynamic Programming Approach ◽

Very low power parallel implementation of stereo vision algorithm on a solar cell powered MIMD many core architecture

2011 Aerospace Conference ◽

10.1109/aero.2011.5747451 ◽

2011 ◽

Cited By ~ 1

Author(s):

Francesco Diotalevi ◽

Amir Fijany ◽

Michael Montvelishsky ◽

Jean-Guy Fontaine

Keyword(s):

Solar Cell ◽

Low Power ◽

Stereo Vision ◽

Parallel Implementation ◽

Many Core ◽