This paper presents a design of a binary comparator circuit using minimum fan-in logic gates (NAND-NOR) for achieving low power-delay-product (PDP). A 2-bit binary comparator circuit is re-designed to minimize fan-in of logic gates. Utilizing the concept of 2–bit comparator, a general gate-level architecture of a comparator system is proposed for higher input operands. A back-tracking model has been proposed in this work to estimate the worst-case performance in terms of delay and power or PDP for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work has also been extended for 20, 16, 14, 10, and 7-nm FINFET technology. The comparator circuits are simulated on Pyxis schematic tool by Mentor Graphics.
Accurate Estimation of Power Consumption for Binary Comparator System using Back Tracking
