A new approach to test generation and test compaction for scan circuits

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253735 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

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Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.819424 ◽

2003 ◽

Vol 22 (12) ◽

pp. 1663-1670 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

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The cell method, a new approach to multiple stuck-at-fault test generation

Microelectronics Reliability ◽

10.1016/0026-2714(80)90272-3 ◽

1980 ◽

Vol 20 (3) ◽

pp. 380

Keyword(s):

Test Generation ◽

New Approach ◽

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Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2014.2358932 ◽

2014 ◽

Vol 33 (12) ◽

pp. 1955-1964 ◽

Author(s):

Irith Pomeranz

Keyword(s):

Static Test ◽

Test Compaction ◽

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An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1109/dac.2001.935495 ◽

2002 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Compaction ◽

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An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1145/378239.378390 ◽

2001 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar Reddy

Keyword(s):

Test Compaction ◽

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Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183159 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

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Static test compaction for diagnostic test sets of full-scan circuits

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2009.0110 ◽

2010 ◽

Vol 4 (5) ◽

pp. 365-373 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

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A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

2006 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2006.313252 ◽

2006 ◽

Author(s):

Tsuyoshi Iwagaki ◽

Satoshi Ohtake ◽

Hideo Fujiwara

Keyword(s):

Test Generation ◽

Generation Model ◽

Partial Scan ◽

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Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

IEEE Transactions on Computers ◽

10.1109/tc.2004.118 ◽

2004 ◽

Vol 53 (12) ◽

pp. 1569-1581 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Lower Bound ◽

Static Test ◽

Test Compaction ◽

Full Scan ◽

Test Sets ◽

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A new approach in the implementation of test generation algorithms for programmable logic arrays

Proceedings of the 39th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1996.594145 ◽

2002 ◽

Author(s):

A. Cruz

Keyword(s):

Test Generation ◽

Programmable Logic ◽

Programmable Logic Arrays ◽

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