For several years, many authors have predicted that nano-scale integrated devices and circuits will have a rising sensitivity to both transient and permanent faults effects. Essentially, there seems to be an emerging demand for building highly dependable hardware / software systems from unreliable components. Most of the effort has so far gone into the detection and compensation of transient fault effects. More recently, also the possibility of repairing permanent faults, due to either production flaws or to wear-out effects after some time of operation in the field of application, needs further investigation. While built-in self test (BIST) and even self repair (BISR) for regular structures such as static memories (SRAMs) is well understood, concepts for in-system repair of irregular logic and interconnects are few and mainly based on field-programmable gate-arrays (FPGAs) as the basic implementation. In this chapter, the authors try to analyse different schemes of logic (self-) repair with respect to cost and limitations, using repair schemes that are not based on FPGAs. It can be shown that such schemes are feasible, but need lot of attention in terms of hidden single points of failure.
ARQUITETURA PARA IDENTIFICAR E ESTIMAR REGIÕES DE FALTAS PERMANENTES EM MÉDIA TENSÃO: UMA CONTRIBUIÇÃO DA PLATAFORMA SMATLVGRID / ARCHITECTURE TO IDENTIFY AND ESTIMATE REGIONS OF PERMANENT FAULTS IN MEDIUM VOLTAGE: A CONTRIBUTION OF THE SMATLVGRID PLATFORM