2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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9781479961559, 9781479961542

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A probabilistic analysis of resilient reconfigurable designs

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962074 ◽

2014 ◽

Cited By ~ 2

Author(s):

A. Malek ◽

S. Tzilis ◽

D. A. Khan ◽

I. Sourdis ◽

G. Smaragdos ◽

...

Keyword(s):

Probabilistic Analysis

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A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962078 ◽

2014 ◽

Cited By ~ 4

Author(s):

In-Seok Jung ◽

Yong-Bin Kim

Keyword(s):

Sar Adc ◽

Calibration Technique ◽

Self Calibration ◽

Capacitor Mismatch

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Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962072 ◽

2014 ◽

Cited By ~ 4

Author(s):

Mario Scholzel ◽

Tobias Koal ◽

Heinrich T. Vierhaus

Keyword(s):

Superscalar Processors ◽

Permanent Faults ◽

Self Test

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Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962098 ◽

2014 ◽

Cited By ~ 5

Author(s):

Jerry Backer ◽

David Hely ◽

Ramesh Karri

Keyword(s):

Design For Test ◽

Security Monitoring ◽

Systems On Chip ◽

On Chip

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A runtime manager for gracefully degrading SoCs

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962106 ◽

2014 ◽

Cited By ~ 3

Author(s):

Stavros Tzilis ◽

Ioannis Sourdis

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Exploration of system availability during software-based self-testing in many-core systems under test latency constraints

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962088 ◽

2014 ◽

Cited By ~ 2

Author(s):

Michael A. Skitsas ◽

Chrysostomos A. Nicopoulos ◽

Maria K. Michael

Keyword(s):

System Availability ◽

Self Testing ◽

Many Core

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A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962077 ◽

2014 ◽

Cited By ~ 1

Author(s):

Yongsuk Choi ◽

Chun-hsiang Chang ◽

In-Seok Jung ◽

Marvin Onabajo ◽

Yong-Bin Kim

Keyword(s):

Low Power ◽

Calibration System

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Fault tolerant and highly adaptive routing for 2D NoCs

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962100 ◽

2014 ◽

Cited By ~ 4

Author(s):

Manoj Kumar ◽

Vijay Laxmi ◽

Manoj Singh Gaur ◽

Masoud Daneshtalab ◽

Masoumeh Ebrahimi ◽

...

Keyword(s):

Fault Tolerant ◽

Adaptive Routing

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Preemptive multi-bit IJTAG testing with reconfigurable infrastructure

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962089 ◽

2014 ◽

Author(s):

Shahrzad Keshavarz ◽

Amirreza Nekooei ◽

Zainalabedin Navabi

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Security methods in fault tolerant modified line graph based networks

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2014.6962104 ◽

2014 ◽

Author(s):

Prashant D. Joshi ◽

Said Hamdioui

Keyword(s):

Fault Tolerant ◽

Line Graph

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2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A probabilistic analysis of resilient reconfigurable designs

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

A runtime manager for gracefully degrading SoCs

Exploration of system availability during software-based self-testing in many-core systems under test latency constraints

A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA

Fault tolerant and highly adaptive routing for 2D NoCs

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure

Security methods in fault tolerant modified line graph based networks

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications