Communications in Computer and Information Science - VLSI Design and Test
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Published By Springer Singapore

9789811074691, 9789811074707

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_44 ◽

2017 ◽

pp. 441-451 ◽

Cited By ~ 1

Author(s):

Ambika Prasad Shah ◽

Nandakishor Yadav ◽

Santosh Kumar Vishvakarma

Keyword(s):

Cmos Circuits ◽

Degradation Monitoring

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An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_56 ◽

2017 ◽

pp. 581-593

Author(s):

Jasmine Kaur Gulati ◽

Bhanu Prakash ◽

Sumit Darak

Keyword(s):

Power Reduction ◽

Clock Tree

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Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_37 ◽

2017 ◽

pp. 376-387

Author(s):

Mamata Panigrahy ◽

Nirmal Chandra Behera ◽

B. Vandana ◽

Indrajit Chakrabarti ◽

Anindya Sundar Dhar

Keyword(s):

Memory Efficient

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Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_22 ◽

2017 ◽

pp. 217-224

Author(s):

Avishek Choudhury ◽

Biplab K. Sikdar

Keyword(s):

Fault Tolerance ◽

Performance Analysis ◽

Chip Multiprocessors ◽

Permanent Faults

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Pseudo-BIST: A Novel Technique for SAR-ADC Testing

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_18 ◽

2017 ◽

pp. 168-178

Author(s):

Yatharth Gupta ◽

Sujay Deb ◽

Vikrant Singh ◽

V. N. Srinivasan ◽

Manish Sharma ◽

...

Keyword(s):

Sar Adc ◽

Novel Technique ◽

Adc Testing

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Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_15 ◽

2017 ◽

pp. 136-143

Author(s):

Sushma Srivastava ◽

S. S. Rathod

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FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_9 ◽

2017 ◽

pp. 75-80

Author(s):

Thilagavathy R ◽

Susmitha Settivari ◽

Venkataramani B ◽

Bhaskar M

Keyword(s):

Fpga Implementation ◽

Area Efficient

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A Cost Effective Technique for Diagnosis of Scan Chain Faults

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_20 ◽

2017 ◽

pp. 191-204 ◽

Cited By ~ 2

Author(s):

Satyadev Ahlawat ◽

Darshit Vaghani ◽

Jaynarayan Tudu ◽

Ashok Suhag

Keyword(s):

Cost Effective ◽

Effective Technique ◽

Cost Effective Technique ◽

Scan Chain

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Multi-mode Toggle Random Access Scan to Minimize Test Application Time

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_21 ◽

2017 ◽

pp. 205-216

Author(s):

Anshu Goel ◽

Rohini Gulve

Keyword(s):

Random Access ◽

Application Time ◽

Test Application Time ◽

Test Application ◽

Multi Mode

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Delay and Frequency Investigations in Coupled MLGNR Interconnects

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_43 ◽

2017 ◽

pp. 429-440

Author(s):

Manish Joshi ◽

Koduri Teja ◽

Ashish Singh ◽

Rohit Dhiman

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Communications in Computer and Information Science - VLSI Design and TestLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Singapore

LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder

Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors

Pseudo-BIST: A Novel Technique for SAR-ADC Testing

Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology

FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT

A Cost Effective Technique for Diagnosis of Scan Chain Faults

Multi-mode Toggle Random Access Scan to Minimize Test Application Time

Delay and Frequency Investigations in Coupled MLGNR Interconnects

Communications in Computer and Information Science - VLSI Design and Test
Latest Publications