Towards a Formal Description Language for Digital IT Consulting Products in Decentralized IT Consulting Firms

2019 ◽  
Author(s):  
Meikel Bode
Keyword(s):  
Formal Description ◽  
Description Language ◽  
Consulting Firms

CADL - A formal description language for parallel computer architectures

1988 ◽  
Vol 24 (1-5) ◽  
pp. 363-370 ◽  
Author(s):  
Ingo Eichenseher ◽  
Theo Ungerer ◽  
Eberhard Zehendner
Keyword(s):  
Computer Architectures ◽  
Parallel Computer ◽  
Formal Description ◽  
Description Language

SDL-TRAN—An interactive generator for formal description language SDL

1996 ◽  
Vol 11 (1) ◽  
pp. 49-60
Author(s):  
Yaoxue Zhang ◽  
Hua Chen ◽  
Yue Zhang ◽  
Guoli Liu
Keyword(s):  
Formal Description ◽  
Description Language

Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation

2019 ◽  
Vol 892 ◽  
pp. 134-142 ◽  
Author(s):  
Wilayat Khan ◽  
Basim Azam ◽  
Noman Shahid ◽  
Abdul Moeed Khan ◽  
Ahtisham Shaheen
Keyword(s):  
Digital Circuits ◽  
Functional Equivalence ◽  
Formal Description ◽  
Hardware Description Languages ◽  
Description Language ◽  
Type Safety ◽  
Hardware Description ◽  
Functional Correctness ◽  
Description Languages ◽  
Mathematical Foundations

To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.

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