Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.

A Real Time Algorithm for Versatile Mode Parking System and Its Implementation on FPGA Board

This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentially exploited for future vehicle generation. A specific mode can be easily computed using the proposed strategy. A variety of candidate modes could be generated using one developed real time VHDL (VHSIC Hardware Description Language) algorithm providing optimal solutions with performance measures. Based on simulation and experimental results, the AVPS is able to find and recognize in advance which parking mode to select. This combination describes full implementation on a mobile robot, such as a car, based on a specific FPGA (Field-Programmable Gate Array) card. To prove the effectiveness of the proposed innovation, an evaluation process comparing the proposed technique with existing techniques was conducted and outlined.

Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

The Concept of Understanding the Social Phenomenon in Its Theoretical Images: From Reconstruction to Scenario Design

This article is devoted to solving the problem of epistemological and ontological insufficiency of traditional scientific approaches applied to the comprehension of social phenomena presented in their disordered, chaotic multidisciplinary theoretical images (interpretations). A comprehensive and in-depth analysis of disciplinary strategies / programs for comprehending social phenomena that serve as the object of scientific views of a number of scientific fields has shown that they demonstrate a pronounced methodological approach, lack of clarity of which description language describes / is able to fully describe their object of scientific knowledge. The key specificity of the problematization of the article is determined by the fact that the focus is on the process / result of reconstructing / constructing theoretical interpretations of a social phenomenon taken in the coordinates of space and time. It is proposed to correlate the following processes with the process of understanding the theoretical interpretations of the studied social phenomenon: reconstruction (past, present) and scenario construction (present, future). The author's analytical position is determined by the fact that theoretical interpretations of the perceived social phenomenon will always belong exclusively to the past and future of its plans, but not to the present. This implicit, but very important facet, unfortunately, escapes in the dominant and well-established theoretical reflection of social phenomena today. The main purpose of this publication is to overcome the above-mentioned difficulties, relying on the proposed universal concept of comprehension of multidisciplinary social phenomena. The author's approach proposed in the publication, based on the idea of understanding the theoretical interpretations of the social phenomenon under study belonging to the world of the past (reconstruction - for understanding the theorizations of its past events) and the future (scenario construction - for reflection on the theoretical pictures of its future events), is designed to overcome the discovered problem. Summarizing, the paper formulated the principles for determining the optimal way to comprehend social phenomena and the key prohibitions dictated by the author's concept of comprehending social phenomena revealed to the researcher in their multidisciplinary interpretations /theorizations.

Design of a BIST implemented AES crypto-processor ASIC

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

The Protean Viewpoint in One Hundred Years of Solitude

Point of view is a primary category of narrative, given that other elements such as characterization, description, language, worldview, structure, and genre, if they are to be convincing, need to be consistent with the adopted vantage point. In One Hundred Years of Solitude, where there is little direct dialogue, a polyvalent and multilayered diegesis, where an uncertain narrator recounts what different characters see, feel, and say, becomes a signature technique. According to Boris Uspensky, the “ideological point of view,” defined as the way of looking at the world conceptually, is not explicitly expressed, but found rather at the phraseological level of the narrative—marking a return to rhetorical criticism. “Many years later, before the firing squad, Colonel Aureliano Buendía would remember that remote afternoon when his father took him to discover ice.” From the outset, the viewpoint is marked by extreme shifts in person, character, time, tenses, and space, mapping its polyphony. This polyvalent narrator shifts from character to character, while the phraseology evokes different genres of the marvelous (myth, legend, folk tales, children’s stories, fairy tales, chronicles, travelogues, and ethnographic accounts). This overlay supports the verisimilitude of magical realist narrative. Ultimately the authorial mask is revealed to be Melquiades, himself a protean figure, a gypsy, merchant, explorer, ethnographer, inspired in Don Quixote’s Cide Hamete Benengeli. The narrator’s worldview coincides with the characters, such that no one shows surprise before the supernatural. The ideology appears naive, provincial, rural, primitive, and akin to outsider art, while maintaining a sophisticated technique.

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.