An algorithm for zero-skew clock tree routing with buffer insertion

Proceedings ED&TC European Design and Test Conference ◽

10.1109/edtc.1996.494154 ◽

2002 ◽

Author(s):

Y.P. Chen ◽

D.F. Wong

Keyword(s):

Buffer Insertion ◽

Tree Routing ◽

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Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles

2015 28th International Conference on VLSI Design ◽

10.1109/vlsid.2015.81 ◽

2015 ◽

Author(s):

Partha Pratim Saha ◽

Sumonto Saha ◽

Tuhina Samanta

Keyword(s):

Buffer Insertion ◽

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A parallel algorithm for zero skew clock tree routing

Proceedings of the 1998 international symposium on Physical design - ISPD '98 ◽

10.1145/274535.274552 ◽

1998 ◽

Author(s):

Zhaoyun Xing ◽

Prithviraj Banerjee

Keyword(s):

Parallel Algorithm ◽

Tree Routing ◽

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Zero Skew Clock-Tree Optimization With Buffer Insertion/Sizing and Wire Sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.825875 ◽

2004 ◽

Vol 23 (4) ◽

pp. 565-572 ◽

Author(s):

J.-L. Tsai ◽

T.-H. Chen ◽

C.C.-P. Chen

Keyword(s):

Buffer Insertion ◽

Tree Optimization ◽

Wire Sizing ◽

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Iterative convergence of optimal wire sizing and available buffer insertion for zero-skew clock tree optimization

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. ◽

10.1109/apccas.2004.1412815 ◽

2005 ◽

Author(s):

Jin-Tai Yan ◽

Chia-Wei Wu ◽

Kai-Ping Lin ◽

Yu-Cheng Lee ◽

Tzu-Ya Wang

Keyword(s):

Buffer Insertion ◽

Tree Optimization ◽

Wire Sizing ◽

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Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

Proceedings of the 2000 international symposium on Physical design - ISPD '00 ◽

10.1145/332357.332370 ◽

2000 ◽

Author(s):

I-Min Liu ◽

Tan-Li Chou ◽

Adnan Aziz ◽

D. F. Wong

Keyword(s):

Buffer Insertion ◽

Tree Construction ◽

Wire Sizing ◽

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Effective legitimate skew driven clock tree routing

2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 ◽

10.1109/icasic.2003.1277509 ◽

2003 ◽

Author(s):

Meng Zhao ◽

Yici Cai ◽

Xianlong Hong ◽

Yi Liu ◽

Liang Huang

Keyword(s):

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Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

Integration ◽

10.1016/j.vlsi.2010.09.002 ◽

2011 ◽

Vol 44 (1) ◽

pp. 87-101 ◽

Author(s):

Chung-Chieh Kuo ◽

Chia-Chun Tsai ◽

Trong-Yen Lee

Keyword(s):

Pattern Matching ◽

Tree Construction ◽

X Architecture ◽

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Zero-Skew Driven for RLC Clock Tree Construction in SoC

Third International Conference on Information Technology and Applications (ICITA'05) ◽

10.1109/icita.2005.315 ◽

2005 ◽

Author(s):

Chia-Chun Tsai ◽

Jan-Ou Wu ◽

Chung-Chieh Kuo ◽

Trong-Yen Lee ◽

Wen-Ta Lee

Keyword(s):

Tree Construction ◽

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Zero skew clock routing for fast clock tree generation

The International Conference on Electrical Engineering ◽

10.21608/iceeng.2008.34322 ◽

2008 ◽

Vol 6 (6) ◽

pp. 1-11

Author(s):

M. Reaz ◽

M. Ibrahimy ◽

F. Mohd-Yasin ◽

A. Mohammad

Keyword(s):

Tree Generation ◽

Clock Routing ◽

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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e91-a.1.365 ◽

2008 ◽

Vol E91-A (1) ◽

pp. 365-374 ◽

Author(s):

C.-C. TSAI ◽

J.-O. WU ◽

T.-Y. LEE

Keyword(s):

Relational Clustering ◽

Tree Construction ◽

Grey Relational ◽

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