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Proceedings ED&TC European Design and Test Conference
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TOTAL DOCUMENTS
106
(FIVE YEARS 0)
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16
(FIVE YEARS 0)
Published By IEEE Comput. Soc. Press
0818674237
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Latest Documents
Most Cited Documents
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Sequential permissible functions and their application to circuit optimization
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494322
◽
2002
◽
Author(s):
Chih-Chang Lin
◽
Kuang-Chien Chen
◽
M. Marek-Sadowska
◽
M. Tien-Chien Lee
Keyword(s):
Circuit Optimization
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Defect-oriented experiments in fault modelling and fault simulation of microsystem components
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494350
◽
2002
◽
Cited By ~ 13
Author(s):
W. Vermeiren
◽
B. Straube
◽
A. Holubek
Keyword(s):
Fault Simulation
◽
Fault Modelling
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Analogue fault modelling and simulation for supply current monitoring
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494354
◽
2002
◽
Cited By ~ 6
Author(s):
M. Zwolinski
◽
C. Chalk
◽
B.R. Wilkins
Keyword(s):
Modelling And Simulation
◽
Fault Modelling
◽
Supply Current
◽
Current Monitoring
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Recursive bipartitioning of signal flow graphs for programmable video signal processors
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494341
◽
2002
◽
Cited By ~ 5
Author(s):
E.H.L. Aarts
◽
G. Essink
◽
E.A. de Kock
Keyword(s):
Video Signal
◽
Signal Flow
◽
Signal Flow Graphs
◽
Signal Processors
◽
Flow Graphs
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Area and timing estimation for lookup table based FPGAs
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494141
◽
2002
◽
Cited By ~ 16
Author(s):
M. Xu
◽
F.J. Kurdahi
Keyword(s):
Lookup Table
◽
Timing Estimation
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Hardware/software partitioning using integer programming
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494343
◽
2002
◽
Cited By ~ 63
Author(s):
R. Niemann
◽
P. Marwedel
Keyword(s):
Integer Programming
◽
Software Partitioning
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A hardware/software codesign case study: design of a robot arm controller
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494363
◽
2002
◽
Author(s):
M. Abid
◽
A. Changuel
◽
A. Jerraya
Keyword(s):
Study Design
◽
Robot Arm
◽
Case Study Design
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Thread-based software synthesis for embedded system design
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494314
◽
2002
◽
Cited By ~ 2
Author(s):
Youngsoo Shin
◽
Kiyoung Choi
Keyword(s):
Embedded System
◽
System Design
◽
Software Synthesis
◽
Embedded System Design
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An algorithm for zero-skew clock tree routing with buffer insertion
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494154
◽
2002
◽
Cited By ~ 30
Author(s):
Y.P. Chen
◽
D.F. Wong
Keyword(s):
Buffer Insertion
◽
Clock Tree
◽
Tree Routing
◽
Zero Skew
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Simulated annealing algorithm with multi-molecule: an approach to analog synthesis
Proceedings ED&TC European Design and Test Conference
◽
10.1109/edtc.1996.494358
◽
2002
◽
Cited By ~ 2
Author(s):
H.Z. Yang
◽
C.Z. Fan
◽
H. Wang
◽
R.S. Liu
Keyword(s):
Simulated Annealing
◽
Simulated Annealing Algorithm
◽
Analog Synthesis
◽
Annealing Algorithm
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