Accurate and efficient small-signal modeling of active devices using artificial neural networks

2002 ◽  
Author(s):  
P.M. Watson ◽  
M. Weatherspoon ◽  
L. Dunleavy ◽  
G.L. Creech
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Small Signal ◽  
Signal Modeling ◽  
Active Devices ◽  
Artificial Neural ◽  
Small Signal Modeling

ANALOG MOS VECTOR MULTIPLIERS FOR THE IMPLEMENTATION OF SYNAPSES IN ARTIFICIAL NEURAL NETWORKS

1991 ◽  
Vol 01 (02) ◽  
pp. 205-228 ◽  
Author(s):  
FATHI M.A. SALAM ◽  
MYUNG-RYUL CHOI
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Large Scale ◽  
Percentage Error ◽  
Small Signal ◽  
Slew Rate ◽  
Mos Transistors ◽  
Maximum Percentage ◽  
Analog Signals ◽  
Artificial Neural

All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 μm CMOS n-well process via MOSIS.

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