Development and Evaluation of a Dual-Layer-Offset PET Detector Constructed with Different Reflectors

Dual-layer-offset or multi-layer-offset design of a PET detector can improve spatial resolution while maintaining high sensitivity. In this study, three dual-layer-offset LYSO detectors with three different reflectors (ESR, Toray, and BaSO4) were developed. The top layer consisted of a 17 × 17 array of crystals 1 × 1 × 6.5 mm3 in size and the bottom layer consisted of an 18 × 18 array of crystals 1 × 1 × 9.5 mm3 in size. Neither light guides nor optical glue were used between the two layers of crystals. A custom-designed electronics system, composed of a 6 × 6 SiPM array, two FPC cables, and a custom-designed data processing module, was used to read out signals. An optimized interaction-decoding algorithm using the center of gravity to determine the position and threshold of analog signals for timing methods was applied to generate decoding flood histograms. The detector performances, in terms of peak to valley ratio of the flood histograms and energy resolutions, were calculated and compared. The dual-layer-offset PET detector constructed with BaSO4 reflectors performed much better than the other two reflectors in both crystal identification and energy resolution. The average peak-to-valley ratio and the energy resolution were approximately 7 and 11%, respectively. In addition, the crystals in the bottom layer showed better performance at crystal identification than those in the top layer. This study can act as a reference providing guidance in choosing scintillator reflectors for multi-layer dedicated DOI detectors designed for small-animal PET imaging.

Measurement of EM field immunity of VCO-based ADCs in 28nm CMOS technology

Internet-of-things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to radio-frequency (RF) disturbances that are essentially present in IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28-nm CMOS 10-bit VCO-ADC prototype exhibit the sensitivity against RF signals in the widely used 2.4 GHz frequency band.

Multichannel ADC IP Core on Xilinx SoC FPGA

Sensing of analogue signals such as voltage, temperature, pressure, current etc. is required to acquire the real time analog signals in the form digital streams. Most of the static analog signals are converted into voltage using sensors, transducers etc. and then measured using ADCs. The digitized samples from ADC are collected either through serial or parallel interface and processed by the programmable chips such as processors, controllers, FPGAs, SOCs etc. In some cases, Multichannel supported ADCs are used to save the layout area when the functionalities are to be realized in a small form factor. In such scenarios, parallel interface for each channel is not a preferred interface considering the more number of interfaces / traces between the components. Hence, Custom, Sink synchronized, Configurable multichannel ADC soft IP core has been developed using VHDL coding to interwork with multichannel supported, time division multiplexed ADCs with serial interface. The developed IP core can be used either as it is with the SPI interface as specified in this paper or with necessary modifications / configurations. The configurations can be the number of channels, sample size, sampling frequency, data transfer clock, type of synchronization – source / sink, control signals and the sequence of the operations performed to configure ADC. The efficiency of implementation is validated using the measurements of throughput, and accuracy for the required range of input with acceptable tolerances. ZYNQ FPGA and LTC2358 ADC are used to evaluate the developed IP core. Integrated Logic Analyser (ILA) which is an integrated verification tool of Vivado is used for Verification.

Determine the parameters of PID algorithm in liquid level control controlled by PLC s7 1500 using 3d virtual reality model

It is very common to stabilize the preset value (Wanted value) of analog signals such as temperature, pressure, weight, flow, speed in automatic control. However, these control objects often have some problems such as overshooting, taking a long time to bring the system to a steady value, and large errors. One of the most used systems to overcome these problems is the PID, which is a preset stabilizing system with a quick function that returns the system to the set value in a short time without overshooting. error is close to zero. However, determining the scale parameters Ki, integral Kp, and differential Kd for the system to work optimally is a problem that needs to be studied. This paper presents how to accurately determine differential, integral, and scale coefficients according to 3D virtual reality model. Used a lot in simulation modeling for training and practical applications.

Digital demodulators for analog signals: comparative analysis and simulation

The paper examines digital demodulators for two commonly used techniques of modulating analog signals: amplitude modulation (AM) and frequency modulation (FM). The described demodulators can be used to perform the radio monitoring of narrowband signal ranges including FM broadcasting stations as well as license-free CB, LPD, PMR bands. The demodulators considered in this work are intended for programmable devices with limited memory and computing resources, for example, for STM32F407 microcontrollers and similar ones. The paper presents the analysis and simulation of demodulators for AM signals, FM signals with low modulation indices and for FM signals without restriction on the modulation indices. In addition, the authors demonstrate how to demodulate the phase-modulation signal using a quadrature demodulator. The number of operations that are available for demodulation is limited by IF multiplication and filtering. The simulation of the analyzed demodulation algorithms was carried out in the Scilab environment which is a free analogue of the Matlab environment. To explain the principle of operation of demodulators, block diagrams and graphs of signals in time and frequency domains are shown.

Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

New application of non-binary Galois fields Fourier transform: digital analog of convolution theorem

It is shown that the use of the representation of digital signals varying in the restricted amplitude range through elements of Galois fields and the Galois field Fourier transform makes it possible to obtain an analogue of the convolution theorem. It is shown that the theorem makes it possible to analyze digital linear systems in same way that is used to analyze linear systems described by functions that take real or complex values (analog signals). In particular, it is possibile to construct a digital analogue of the transfer function for any linear system that has the property of invariance with respect to the time shift. It is shown that the result obtained has a fairly wide application, in particular, it is of interest for systems in which signal processing methods are combined with the use of neural networks.

Designing of an algebraic signature analyzer for mixed-signal systems and testing

While the design of signature analyzers for digital circuits has been well researched in the past, the common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. We offer a method to designing an algebraic signature analyzer that can be used for mixed-signal systems testing. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in algebraic coding and cryptography.