Reconstruction filter for Delta-Sigma oversampling digital-to-analog converter implemented in 0.18um CMOS technology

2015 ◽  
Author(s):  
Olga Joy L. Gerasta ◽  
Ace Virgil D. Villaruz
Keyword(s):  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Delta Sigma ◽  
Analog Converter ◽  
Reconstruction Filter ◽  
Digital To Analog

scholarly journals Design of low power 10GS/s 6-Bit DAC using CMOS technology

2017 ◽  
Vol 7 (1.5) ◽  
pp. 226 ◽  
Author(s):  
P. Ramakrishna ◽  
K Hari Kishore
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Low Voltage ◽  
Cmos Technology ◽  
Dynamic Threshold ◽  
Digital To Analog Converter ◽  
Digital To Analog Converters ◽  
Analog Converter ◽  
Digital To Analog

A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the    R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

scholarly journals A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 464 ◽  
Author(s):  
Wang ◽  
Guo ◽  
Zhou ◽  
Wu ◽  
Luan ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Current Steering ◽  
Hardware Complexity ◽  
Digital To Analog Converter ◽  
Switching Current ◽  
Analog Converter ◽  
Digital To Analog

A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

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