A New 4D Hyperchaotic System and Its Analog and Digital Implementation

This work presents a new four-dimensional autonomous hyperchaotic system based on Méndez-Arellano-Cruz-Martínez (MACM) 3D chaotic system. Analytical and numerical studies of the dynamic properties are conducted for the new hyperchaotic system (NHS) in its continuous version (CV), where the Lyapunov exponents are calculated. The CV of the NHS is simulated and implemented using operational amplifiers (OAs), whereas the Discretized Version (DV) is simulated and implemented in real-time. Besides, a novel study of the algorithm performance of the proposed DV of NHS is conducted with the digital-electronic implementation of the floating-point versus Q1.15 fixed-point format by using the Digital Signal Processor (DSP) engine of a 16-bit dsPIC microcontroller and two external dual digital to analog converters (DACs) in an embedded system (ES).

Deconstructing the Ethernet with ChokyFop

The analysis of digital-to-analog converters is an unproven challenge. After years of confirmed research into flip-flop gates, we prove the analysis of systems, which embodies the compelling principles of programming languages. In our research we propose a novel algorithm for the refinement of multi-processors (ChokyFop), confirming that information re- trieval systems can be made relational, wireless, and constant- time.

Digital Potentiometers and Digital-to-Analog Converters in Tasks for Tuning Of Active RC-Filters

The most popular schemes of digital potentiometers (DP) and digital-to-analog converters (DAC) are considered. DP and DAC use how elements of parameter adjustment of active RC-filters. The circuits of the DAC on the Kelvin-Varley divider, the Kelvin divider based on the R-2R matrix, and the architecture of the DAC with a segmented circuit are shown. The internal structure of DP an Analog Devices and Intersil company is shown, and also the DP switching circuits in a tunable low-pass filter and a band-pass filter, a programmable inverting amplifier and a voltage regulator are presented.

Analysis and Optimization for Downlink Cell-Free Massive MIMO System with Mixed DACs

This paper concentrates on the rate analysis and optimization for a downlink cell-free massive multi-input multi-output (MIMO) system with mixed digital-to-analog converters (DACs), where some of the access points (APs) use perfect-resolution DACs, while the others exploit low-resolution DACs to reduce hardware cost and power consumption. By using the additive quantization noise model (AQNM) and conjugate beamforming receiver, a tight closed-form rate expression is derived based on the standard minimum mean square error (MMSE) channel estimate technique. With the derived result, the effects of the number of APs, the downlink transmitted power, the number of DAC bits, and the proportion of the perfect DACs in the mixed-DAC architecture are conducted. We find that the achievable sum rate can be improved by increasing the proportion of the perfect DACs and deploying more APs. Besides, when the DAC resolution arrives at 5-bit, the system performance will invariably approach the case of perfect DACs, which indicates that we can use 5-bit DACs to substitute the perfect DACs. Thus, it can greatly reduce system hardware cost and power consumption. Finally, the weighted max–min power allocation scheme is proposed to guarantee that the users with high priority have a higher rate, while the others are served with the same rate. The simulation results prove the proposed scheme can be effectively solved by the bisection algorithm.