AnyCore-1: A comprehensively adaptive 4-way superscalar processor

2016 IEEE Hot Chips 28 Symposium (HCS) ◽

10.1109/hotchips.2016.7936237 ◽

2016 ◽

Author(s):

Rangeen Basu Roy Chowdhury ◽

Anil K. Kannepalli ◽

Eric Rotenberg

Keyword(s):

Superscalar Processor

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An optimal instruction scheduler for superscalar processor

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/71.372778 ◽

1995 ◽

Vol 6 (3) ◽

pp. 303-313 ◽

Author(s):

Hong-Chich Chou ◽

Chung-Ping Chung

Keyword(s):

Superscalar Processor ◽

Instruction Scheduler

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Evaluating the Impact of Fault Recovery on Superscalar Processor Performance

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06) ◽

10.1109/prdc.2006.33 ◽

2006 ◽

Author(s):

Toshinori Sato ◽

Akihiro Chiyonobu

Keyword(s):

Fault Recovery ◽

Superscalar Processor ◽

Processor Performance ◽

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Scheduling on a superscalar processor using the chain technique

Proceedings of the 2014 International Conference on Advanced Mechatronic Systems ◽

10.1109/icamechs.2014.6911578 ◽

2014 ◽

Author(s):

Lin Meng ◽

Nobihiro Moriwaki ◽

Shigeru Oyanagi

Keyword(s):

Superscalar Processor

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Reconfigurable Dynamic Scheduling In Superscalar Processor for FIR Filter

2017 14th IEEE India Council International Conference (INDICON) ◽

10.1109/indicon.2017.8487498 ◽

2017 ◽

Author(s):

S Ramya ◽

B. Rajeshwari

Keyword(s):

Dynamic Scheduling ◽

Superscalar Processor

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A framework for statistical modeling of superscalar processor performance

Proceedings Third International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1997.569691 ◽

2002 ◽

Author(s):

D.B. Noonburg ◽

J.P. Shen

Keyword(s):

Statistical Modeling ◽

Superscalar Processor ◽

Processor Performance

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Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_5 ◽

2005 ◽

pp. 40-48

Author(s):

Guadalupe Miñana ◽

Oscar Garnica ◽

José Ignacio Hidalgo ◽

Juan Lanchares ◽

José Manuel Colmenar

Keyword(s):

Power Reduction ◽

Superscalar Processor ◽

Functional Units

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A microarchitecture of clustered superscalar processor

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415561 ◽

2007 ◽

Author(s):

Yang Bing ◽

Mao Zhigang ◽

Gan Chuhui

Keyword(s):

Superscalar Processor

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Design of a superscalar processor based on queue machine computation model

1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368) ◽

10.1109/pacrim.1999.799499 ◽

2003 ◽

Author(s):

S. Okamoto ◽

H. Suzuki ◽

A. Maeda ◽

M. Sowa

Keyword(s):

Computation Model ◽

Machine Computation ◽

Superscalar Processor

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Theoretical modeling of superscalar processor performance

Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture ◽

10.1145/192724.192730 ◽

1994 ◽

Author(s):

Derek B. Noonburg ◽

John P. Shen

Keyword(s):

Theoretical Modeling ◽

Superscalar Processor ◽

Processor Performance

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Analysing superscalar processor architectures with coloured Petri nets

International Journal on Software Tools for Technology Transfer ◽

10.1007/s100090050026 ◽

1998 ◽

Vol 2 (2) ◽

pp. 182-191 ◽

Author(s):

F.P. Burns ◽

A.M. Koelmans ◽

A.V. Yakovlev

Keyword(s):

Coloured Petri Nets ◽

Superscalar Processor ◽

Processor Architectures

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