FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless Applications

2021 ◽  
Author(s):  
Lajwanti Singh ◽  
Geetanjali ◽  
Rajesh Mehra
Keyword(s):  
Distributed Arithmetic ◽  
Wireless Applications ◽  
Arithmetic Algorithm

scholarly journals Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

2016 ◽  
pp. 90-95
Author(s):  
M. Suhasini ◽  
K. Prabhu Kumar ◽  
P. Srinivas
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Performance Estimation ◽  
Switching Activity ◽  
Distributed Arithmetic ◽  
Hybrid Type ◽  
Arithmetic Algorithm ◽  
Overall Performance ◽  
Sign Extension ◽  
And Performance

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion

Complexity ◽  
2005 ◽  
Vol 11 (1) ◽  
pp. 24-29
Author(s):  
T. Salim ◽  
J. Devlin ◽  
J. Whittington ◽  
M. I. Bhatti
Keyword(s):  
Fpga Implementation ◽  
Distributed Arithmetic ◽  
Arithmetic Algorithm

New Distributed Arithmetic Algorithm for Low-Power FIR Filter Implementation

2004 ◽  
Vol 11 (5) ◽  
pp. 463-466 ◽  
Author(s):  
S. Hwang ◽  
G. Han ◽  
S. Kang ◽  
J. Kim
Keyword(s):  
Low Power ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Arithmetic Algorithm
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