scholarly journals Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

2016 ◽  
pp. 90-95
Author(s):  
M. Suhasini ◽  
K. Prabhu Kumar ◽  
P. Srinivas
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Performance Estimation ◽  
Switching Activity ◽  
Distributed Arithmetic ◽  
Hybrid Type ◽  
Arithmetic Algorithm ◽  
Overall Performance ◽  
Sign Extension ◽  
And Performance

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

2021 ◽  
Vol 12 ◽  
pp. 1-8
Author(s):  
Sujata A. A ◽  
Lalitha. Y. S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Software Tool ◽  
Cmos Technology ◽  
Effective Control ◽  
Low Area ◽  
Area Reduction ◽  
And Performance ◽  
Artificial Neural Network Ann ◽  
Universal Gates

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

scholarly journals A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

2011 ◽  
pp. 196-202
Author(s):  
P.Sasi Bala ◽  
S. Raghavendra
Keyword(s):  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Alpha Power ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance ◽  
Least Significant Bits

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic.By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai’s alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

2015 ◽  
Vol 24 (10) ◽  
pp. 1550159 ◽  
Author(s):  
Ramin Razmdideh ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Switching Activity ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Controlled Switching ◽  
Simulation Results

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

scholarly journals FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm

2021 ◽  
Vol 15 ◽  
pp. 690-699
Author(s):  
D Anil Kumar
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Software Tool ◽  
Cmos Technology ◽  
Effective Control ◽  
Low Area ◽  
Area Reduction ◽  
And Performance ◽  
Artificial Neural Network Ann ◽  
Universal Gates

The recent technologies in VLSI chips has grown in terms of scaling of transistor and device parameters but still there is a challenging task for controlling of current between source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip manufacturing, through which current can be effectively controlled. This section addresses the issues present in CMOS technology and majorly concentrated on proposed 4-bit Nano processor using FinFET 32nm technology by using Cadence Virtuoso software tool. In the proposed Nanoprocessor design, the first portion of the design is done using 4bit ALU which includes all basic and universal gates, high speed adder, multiplier and multiplexer. The Carry Save Adder (CSA) and multiplier are the major sub component which can optimize the power consumption and area reduction. The second portion of the proposed Nano processor design is 4-bit 6T SRAM and encoder and decoder and also using Artificial Neural Network (ANN). All these sub components are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS and at the last chip level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET using technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% with optimization in power dissipation of 47% along with optimization in leakage current, with 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses are compressed subsequently respectively. The basic gates, universal gates, CSA, subtraction and MUX are integrated for 4-bit ALU design and its delay, power consumption and area are found to be 0.104nsec, 314.4uW and 56.8μsqm respectively.

scholarly journals Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm

2011 ◽  
Vol 25 (7) ◽  
pp. 26-32 ◽  
Author(s):  
Narendra Singh Pal ◽  
Harjit Pal Singh ◽  
R.K. Sarin ◽  
Sarabjeet Singh
Keyword(s):  
High Speed ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Arithmetic Algorithm

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

2014 ◽  
Vol 23 (07) ◽  
pp. 1450092 ◽  
Author(s):  
PRABIR SAHA ◽  
DEEPAK KUMAR ◽  
PARTHA BHATTACHARYYA ◽  
ANUP DANDAPAT
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Boolean Logic ◽  
Dynamic Power ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Layout Area ◽  
And Performance

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology

2015 ◽  
Vol 33 ◽  
pp. 126-136
Author(s):  
Amin Vanak ◽  
Reza Sabbaghi-Nadooshan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Sequential Circuits ◽  
Fall Time ◽  
And Performance ◽  
Combinational And Sequential Circuits

In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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