Path-based timing optimization by buffer insertion with accurate delay model

2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 ◽

10.1109/icasic.2003.1277497 ◽

2003 ◽

Author(s):

Yiqian Zhang ◽

Qiang Zhou ◽

Xianlong Hong ◽

Yici Cai

Keyword(s):

Delay Model ◽

Buffer Insertion ◽

Timing Optimization ◽

Accurate Delay Model

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Power supply noise in accurate delay model for the sub-threshold domain

Integration ◽

10.1016/j.vlsi.2015.02.001 ◽

2015 ◽

Vol 50 ◽

pp. 127-136

Author(s):

Pasquale Corsonello ◽

Fabio Frustaci ◽

Stefania Perri

Keyword(s):

Power Supply ◽

Delay Model ◽

Power Supply Noise ◽

Supply Noise ◽

Accurate Delay Model

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Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization

17th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2012.6164988 ◽

2012 ◽

Author(s):

Yen-Hung Lin ◽

Yun-Jian Lo ◽

Hian-Syun Tong ◽

Wen-Hao Liu ◽

Yih-Lang Li

Keyword(s):

Massively Parallel ◽

Buffer Insertion ◽

Timing Optimization

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Traffic Signal Timing Optimization by Modelling the Lost Time Effect in the Shock Wave Delay Model

International Conference on Transportation and Development 2016 ◽

10.1061/9780784479926.037 ◽

2016 ◽

Author(s):

Mohammad Noaeen ◽

Amir Abbas Rassafi ◽

Behrouz Homayoun Far

Keyword(s):

Traffic Signal ◽

Time Effect ◽

Signal Timing ◽

Delay Model ◽

Timing Optimization ◽

Signal Timing Optimization ◽

Lost Time ◽

Traffic Signal Timing

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Performance-Driven Routing Tree Construction with Buffer Insertion, Wire Sizing under RLC Delay Model

2007 International Conference on Mechatronics and Automation ◽

10.1109/icma.2007.4304112 ◽

2007 ◽

Author(s):

Chang Qi ◽

Gao-feng Wang ◽

Yue-hua Chen

Keyword(s):

Delay Model ◽

Buffer Insertion ◽

Tree Construction ◽

Routing Tree ◽

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Optimal wire sizing and buffer insertion for low power and a generalized delay model

IEEE Journal of Solid-State Circuits ◽

10.1109/4.494206 ◽

1996 ◽

Vol 31 (3) ◽

pp. 437-447 ◽

Author(s):

J. Lillis ◽

Chung-Kuan Cheng ◽

T.-T.Y. Lin

Keyword(s):

Low Power ◽

Delay Model ◽

Buffer Insertion ◽

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A fast buffered routing tree construction algorithm under accurate delay model

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design ◽

10.1109/icvd.2005.10 ◽

2005 ◽

Author(s):

Yibo Wang ◽

Yici Cai ◽

Xianlong Hong

Keyword(s):

Delay Model ◽

Construction Algorithm ◽

Tree Construction ◽

Routing Tree ◽

Accurate Delay Model

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Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206221 ◽

2003 ◽

Author(s):

R. Bashirullah ◽

Wentai Liu ◽

R. Cavin

Keyword(s):

Experimental Verification ◽

Delay Model ◽

Voltage Mode ◽

Current Voltage ◽

On Chip ◽

Accurate Delay Model

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A More Accurate Delay Model based Task Scheduling in Cellular Edge Computing Systems

2019 IEEE 5th International Conference on Computer and Communications (ICCC) ◽

10.1109/iccc47050.2019.9064217 ◽

2019 ◽

Author(s):

Yuan Zhang ◽

Mingyang Xie

Keyword(s):

Task Scheduling ◽

Edge Computing ◽

Delay Model ◽

Computing Systems ◽

Model Based ◽

Accurate Delay Model

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An Accurate Delay Model For BiCMOS Gates and Off-Chip Drivers

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.692953 ◽

2005 ◽

Author(s):

S.H.K. Embabi ◽

R. Damodaran ◽

R. Bhagwan ◽

D.E. Ross

Keyword(s):

Delay Model ◽

Accurate Delay Model

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An Accurate Delay Model with Consideration of Coupled Queues Effect for Nonsaturated IEEE 802.11 Wireless Networks

International Journal of Information Processing and Management ◽

10.4156/ijipm.vol2.issue3.7 ◽

2011 ◽

Vol 2 (3) ◽

pp. 52-64 ◽

Author(s):

An Song ◽

Shan Wang ◽

Haitao Zhao ◽

Jibo Wei ◽

Mingche Lai

Keyword(s):

Wireless Networks ◽

Ieee 802.11 ◽

Delay Model ◽

Ieee 802.11 Wireless Networks ◽

Accurate Delay Model

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