A low power buffer-aided vector register file for LTE baseband signal processing

Author(s):  
Zhiguo Liu ◽  
Ziyuan Zhu ◽  
Jinglin Shi ◽  
Jinbao Liu ◽  
Shiqiang Li
IEEE Network ◽  
1991 ◽  
Vol 5 (6) ◽  
pp. 39-43 ◽  
Author(s):  
K.M. Duch

2021 ◽  
pp. 42-51
Author(s):  
Angelo Manco ◽  
◽  
Vittorio U. Castrillo

In the framework of modern Unmanned Aerial System (UAS) ground-board communications, a data-link system should provide with the following features [1]: multiband and adaptive modulations for responding to channel conditions changes and multi-standard interoperability, interferences resilience with a secure physical layer, incorporation of an air-to-air link complementary to the classical air-to-ground links. Varying the available communication functions to provide the above features without the need to substitute on-board components is a desired target. For this purpose, a Field Programmable Gate Aray (FPGA) scalable Software Defined Radio hardware Platform (SDRP) and its control and baseband signal processing architecture have been developed. The platform is composed by means of three boards which provide respectively the power supply, an FPGA based processing core and the radio frequency front-end. The control and baseband signal processing architecture, implemented on the FPGA, is designed with an application-independent section, working as a base reference design, and a reconfigurable section that implements communication functions and algorithms. The overall platform, at the board and FPGA architecture level, has been designed considering scalability and modularity as key features. Thanks to this platform a data-link which responds to the above target can be easily implemented. As a case study a reconfigurable data-link between a UAS and a Ground Control Station (GCS), designed to establish reliable communication in all the phases of a flight (parking, taxiing, taking off, cruising and landing), is presented.


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