An FPGA Scalable Software-Defined Radio Platform for UAS Communications Research

In the framework of modern Unmanned Aerial System (UAS) ground-board communications, a data-link system should provide with the following features [1]: multiband and adaptive modulations for responding to channel conditions changes and multi-standard interoperability, interferences resilience with a secure physical layer, incorporation of an air-to-air link complementary to the classical air-to-ground links. Varying the available communication functions to provide the above features without the need to substitute on-board components is a desired target. For this purpose, a Field Programmable Gate Aray (FPGA) scalable Software Defined Radio hardware Platform (SDRP) and its control and baseband signal processing architecture have been developed. The platform is composed by means of three boards which provide respectively the power supply, an FPGA based processing core and the radio frequency front-end. The control and baseband signal processing architecture, implemented on the FPGA, is designed with an application-independent section, working as a base reference design, and a reconfigurable section that implements communication functions and algorithms. The overall platform, at the board and FPGA architecture level, has been designed considering scalability and modularity as key features. Thanks to this platform a data-link which responds to the above target can be easily implemented. As a case study a reconfigurable data-link between a UAS and a Ground Control Station (GCS), designed to establish reliable communication in all the phases of a flight (parking, taxiing, taking off, cruising and landing), is presented.

Polar Code decoder exploration framework

The increasing demand for fast wireless communications requires sophisticated baseband signal processing. One of the computational intense tasks here is advanced Forward Error Correction (FEC), especially the decoding. Finding efficient hardware implementations for sophisticated FEC decoding algorithms that fulfill throughput demands under strict implementation constraints is an active research topic due to increasing throughput, low latency, and high energy efficiency requirements. This paper focuses on the interesting class of Polar Codes that are currently a hot topic. We present a modular framework to automatically generate and evaluate a wide range of Polar Code decoders, with emphasis on design space exploration for efficient hardware architectures. To demonstrate the efficiency of our framework a very high throughput Soft Cancellation (SCAN) Polar Code decoder is shown that was automatically generated. This decoder is, to the best of our knowledge, the fastest SCAN Polar Code decoder published so far.

Generalised Theory on the Effects of Sampling Frequency on GNSS Code Tracking

Synchronisation of the received Pseudorandom (PRN) code and its locally generated replica is fundamental when estimating user position in Global Navigation Satellite System (GNSS) receivers. It has been observed through experiments that user position accuracy decreases if sampling frequency is an integer multiple of the nominal code rate. This paper provides an accuracy analysis based on the number of samples and the residual code phase of each code chip. The outcomes reveal that the distribution of residual code phases in the code phase range [0, 1/ns), where ns is the number of samples per code chip, is the root cause of accuracy degradation, rather than the ratio between sampling frequency and nominal code rate. Doppler frequencies, coherent integration periods, front-end filter bandwidths and received Carrier to Noise ratios (C/N0) also influence receiver accuracy. Also provided are a sampling frequency selection guideline and new proposed estimates of the correlation output and the Delay Locked Loop (DLL) tracking error, which can be applied to precisely model GNSS receiver baseband signal processing.