2010 International Symposium on System on Chip
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Published By IEEE

9781424482795

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625566 ◽

2010 ◽

Cited By ~ 6

Author(s):

Sandeep Pande ◽

Fearghal Morgan ◽

Seamus Cawley ◽

Brian McGinley ◽

Snaider Carrillo ◽

...

Keyword(s):

Neural Network ◽

Network Architectures ◽

Spiking Neural Network ◽

Neural Network Architectures

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Energy-aware run-time mapping for homogeneous NoC

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625542 ◽

2010 ◽

Cited By ~ 3

Author(s):

Guang Sun ◽

Yong Li ◽

Yuanyuan Zhang ◽

Li Su ◽

Depeng Jin ◽

...

Keyword(s):

Energy Aware ◽

Run Time

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Heap access optimizations for a hardware-accelerated Java virtual machine

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625548 ◽

2010 ◽

Author(s):

Joonas Tyystjarvi ◽

Tero Santti ◽

Juha Plosila

Keyword(s):

Virtual Machine ◽

Java Virtual Machine

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Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625531 ◽

2010 ◽

Author(s):

A. Ghofrani ◽

F. Javaheri ◽

S. Safari ◽

Z. Navabi

Keyword(s):

Particle Swarm Optimization ◽

Particle Swarm ◽

Swarm Optimization ◽

Automatic Selection ◽

Selection Of

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Homogeneous MPSoC as baseband signal processing engine for OFDM systems

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625562 ◽

2010 ◽

Cited By ~ 13

Author(s):

Roberto Airoldi ◽

Fabio Garzia ◽

Omer Anjum ◽

Jari Nurmi

Keyword(s):

Signal Processing ◽

Ofdm Systems ◽

Baseband Signal ◽

Baseband Signal Processing ◽

Processing Engine

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Efficient floating-point texture decompression

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625555 ◽

2010 ◽

Author(s):

Tomi Aarnio ◽

Claudio Brunelli ◽

Timo Viitanen

Keyword(s):

Floating Point

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Correct and energy-efficient design of SoCs: The H.264 encoder case study

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625558 ◽

2010 ◽

Cited By ~ 3

Author(s):

Adolf Abdallah ◽

Abdoulaye Gamatie ◽

Jean-Luc Dekeyser

Keyword(s):

Energy Efficient ◽

Efficient Design ◽

Energy Efficient Design

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Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625536 ◽

2010 ◽

Cited By ~ 3

Author(s):

Vladimir Guzma ◽

Teemu Pitkanen ◽

Jarmo Takala

Keyword(s):

Energy Consumption ◽

Scheduling Analysis ◽

Instruction Memory

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State chart refinement validation from approximately timed to cycle callable models

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625551 ◽

2010 ◽

Author(s):

Rainer Findenig ◽

Wolfgang Ecker

Keyword(s):

State Chart

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Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip

2010 International Symposium on System on Chip ◽

10.1109/issoc.2010.5625539 ◽

2010 ◽

Cited By ~ 1

Author(s):

Alessandro Strano ◽

Carles Hernandez ◽

Federico Silla ◽

Davide Bertozzi

Keyword(s):

Process Variation ◽

Networks On Chip ◽

On Chip

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2010 International Symposium on System on ChipLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures

Energy-aware run-time mapping for homogeneous NoC

Heap access optimizations for a hardware-accelerated Java virtual machine

Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization

Homogeneous MPSoC as baseband signal processing engine for OFDM systems

Efficient floating-point texture decompression

Correct and energy-efficient design of SoCs: The H.264 encoder case study

Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis

State chart refinement validation from approximately timed to cycle callable models

Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip

2010 International Symposium on System on Chip
Latest Publications