CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy

Mapping Intimacies ◽

10.1109/iccd53106.2021.00031 ◽

2021 ◽

Author(s):

Jiafeng Xie ◽

Pengzhou He ◽

Chiou-Yng Lee

Keyword(s):

High Performance ◽

Fpga Implementation ◽

Processing Strategy ◽

Polynomial Multiplication

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Erratum: A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(p) [IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E98.A (2015) , No. 3 pp.863-869]

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e98.a.1057_e1 ◽

2015 ◽

Vol E98.A (4) ◽

pp. 1057_e1-1057_e1

Author(s):

Xiang FENG ◽

Shuguo LI

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

High Performance ◽

Fpga Implementation

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Processing strategy for symmetrical ablation profile in pulsed laser patterning of high-performance broadband spiral antennas

Optics & Laser Technology ◽

10.1016/j.optlastec.2021.107211 ◽

2021 ◽

Vol 142 ◽

pp. 107211

Author(s):

Jian-wei Ma ◽

Xing-kun Cao ◽

Dong-xu Han ◽

Jian Wang ◽

Wen-wen Jiang

Keyword(s):

High Performance ◽

Pulsed Laser ◽

Processing Strategy ◽

Spiral Antennas ◽

Laser Patterning ◽

Ablation Profile

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Design and FPGA Implementation of High Performance 8-BIT Vedic Multiplier Using Reversible Logic Based Barrel Shifter

Proceedings of Second International Conference on Signal Processing, Image Processing and VLSI ◽

10.3850/978-981-09-6200-5_vlsi-74 ◽

2015 ◽

Author(s):

Abhilasha . ◽

Sudharshan . ◽

S.L. Anusha

Keyword(s):

High Performance ◽

Reversible Logic ◽

Fpga Implementation ◽

Vedic Multiplier ◽

Barrel Shifter

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High-performance FPGA implementation of packet reordering for multiple TCP connections

2011 11th International Symposium on Communications & Information Technologies (ISCIT) ◽

10.1109/iscit.2011.6089757 ◽

2011 ◽

Author(s):

Feng Zhou ◽

Qingsheng Hu

Keyword(s):

High Performance ◽

Fpga Implementation ◽

Packet Reordering ◽

Tcp Connections

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High-performance FPGA implementation of DES using a novel method for implementing the key schedule

IEE Proceedings - Circuits Devices and Systems ◽

10.1049/ip-cds:20030574 ◽

2003 ◽

Vol 150 (5) ◽

pp. 373 ◽

Cited By ~ 24

Author(s):

M. McLoone ◽

J.V. McCanny

Keyword(s):

High Performance ◽

Fpga Implementation ◽

Key Schedule ◽

Novel Method

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High-Performance FPGA Implementation of Elliptic Curve Cryptography Processor over Binary Field GF(2^163)

Proceedings of the 2nd International Conference on Information Systems Security and Privacy ◽

10.5220/0005741604150422 ◽

2016 ◽

Cited By ~ 1

Author(s):

Md Selim Hossain ◽

Ehsan Saeedi ◽

Yinan Kong

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

High Performance ◽

Fpga Implementation ◽

Binary Field

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A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

Journal of Signal Processing Systems ◽

10.1007/s11265-016-1201-y ◽

2016 ◽

Vol 88 (2) ◽

pp. 107-125 ◽

Cited By ~ 1

Author(s):

Konstantinos Maragos ◽

Christos Spatharakis ◽

George Lentaris ◽

Panagiotis Kontzilas ◽

Stefanos Dris ◽

...

Keyword(s):

Optical Interconnects ◽

High Performance ◽

Fpga Implementation ◽

Feed Forward

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Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance

International Journal of Computer Science and Information Technology ◽

10.5121/ijcsit.2011.3408 ◽

2011 ◽

Vol 3 (4) ◽

pp. 101-110 ◽

Cited By ~ 1

Author(s):

Shabana Aqueel ◽

Kavita Khare

Keyword(s):

High Performance ◽

Fpga Implementation ◽

Sdram Controller

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FPGA Implementation of high performance entropy encoder for H.264 Video CODEC

10.24001/ijaems.icsesd2017.139 ◽

2017 ◽

Author(s):

Prof. Anil Bavaskar ◽

Ms. Prajakta Bhagde

Keyword(s):

High Performance ◽

Fpga Implementation ◽

Video Codec

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Morpheo: A high-performance processor generator for a FPGA implementation

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP) ◽

10.1109/dasip.2011.6136849 ◽

2011 ◽

Cited By ~ 2

Author(s):

Mathieu Rosiere ◽

Jean-Lou Desbarbieux ◽

Nathalie Drach ◽

Franck Wajsburt

Keyword(s):

High Performance ◽

Fpga Implementation

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