FPGA Implementation of high performance entropy encoder for H.264 Video CODEC

Author(s):  
Prof. Anil Bavaskar ◽  
Ms. Prajakta Bhagde
2016 ◽  
Vol 88 (2) ◽  
pp. 107-125 ◽  
Author(s):  
Konstantinos Maragos ◽  
Christos Spatharakis ◽  
George Lentaris ◽  
Panagiotis Kontzilas ◽  
Stefanos Dris ◽  
...  

1998 ◽  
Vol 5 (45) ◽  
Author(s):  
Morten Vadskær Jensen ◽  
Brian Nielsen

We present the design and implementation of a high performance layered video codec, designed for deployment in bandwidth heterogeneous networks. The codec combines wavelet based subband decomposition and discrete cosine transforms to facilitate layered spatial and SNR (signal-to-noise ratio) coding for bit-rate adaptation to a wide range of receiver capabilities. We show how a test video stream can be partitioned into several distinct layers of increasing visual quality and bandwidth requirements, with the difference between highest and lowest requirement being 47 : 1. Through the use of the Visual Instruction Set on SUN's Ultra-SPARC platform we demonstrate how SIMD parallel image processing enables real-time layered encoding and decoding in software. Our 384 * 320 * 24-bit test video stream is partitioned into 21 layers at a speed of 39 frames per second and reconstructed at 28 frames per second. Our VIS accelerated encoder stages are about 3-4 times as fast as an optimized C version. We find that this speed-up is well worth the extra implementation effort.


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