scholarly journals Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance

Author(s):  
Shabana Aqueel ◽  
Kavita Khare
2016 ◽  
Vol 88 (2) ◽  
pp. 107-125 ◽  
Author(s):  
Konstantinos Maragos ◽  
Christos Spatharakis ◽  
George Lentaris ◽  
Panagiotis Kontzilas ◽  
Stefanos Dris ◽  
...  

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Péter Szántó ◽  
Gábor Szedő ◽  
Béla Fehér

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.


Sign in / Sign up

Export Citation Format

Share Document