Voltage and frequency island optimizations for many-core/networks-on-chip designs

2010 ◽  
Author(s):  
Wooyoung Jang ◽  
Duo Ding ◽  
David Z. Pan
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
On Chip ◽  
Many Core

scholarly journals Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip

2018 ◽  
Vol 68 ◽  
pp. 581-602 ◽  
Author(s):  
Md Farhadur Reza ◽  
Dan Zhao ◽  
Hongyi Wu ◽  
Magdy Bayoumi
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
On Chip ◽  
Many Core

scholarly journals A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 613
Author(s):  
Fen Ge ◽  
Chenchen Cui ◽  
Fang Zhou ◽  
Ning Wu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Optimal Placement ◽  
Networks On Chip ◽  
Core Networks ◽  
Application Mapping ◽  
Mapping Approach ◽  
On Chip ◽  
The One ◽  
Multi Phase ◽  
Many Core

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip

2013 ◽  
Vol 37 (4-5) ◽  
pp. 460-471 ◽  
Author(s):  
Bo Yang ◽  
Liang Guang ◽  
Tero Säntti ◽  
Juha Plosila
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
Bounded Number ◽  
On Chip ◽  
Many Core

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 ◽  
Author(s):  
Dexue Zhang ◽  
Xiaoyang Zeng ◽  
Zongyan Wang ◽  
Weike Wang ◽  
Xinhua Chen
Keyword(s):  
Networks On Chip ◽  
Virtual Platform ◽  
On Chip ◽  
Many Core

Implementation and Evaluation of Skip-Links

2011 ◽  
Vol 2 (3) ◽  
pp. 21-49 ◽  
Author(s):  
Simon J. Hollis ◽  
Chris Jackson
Keyword(s):  
Long Range ◽  
Switching Activity ◽  
Traffic Patterns ◽  
Hop Count ◽  
Core Networks ◽  
Mesh Topology ◽  
Node Network ◽  
On Chip ◽  
Many Core ◽  
Prior Analysis

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

Software Defined Networks-on-Chip for Multi/Many-Core Systems

2016 ◽  
Author(s):  
R. Sandoval-Arechiga ◽  
R. Parra-Michel ◽  
J. L. Vazquez-Avila ◽  
J. Flores-Troncoso ◽  
S. Ibarra-Delgado
Keyword(s):  
Software Defined Networks ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

scholarly journals Algoritmo Kmeans para Mapeamento Estático de Processos em Redes-em-Chip

2014 ◽  
Author(s):  
Cíntia Avelar ◽  
Pedro Penna ◽  
Henrique Freitas
Keyword(s):  
Networks On Chip ◽  
On Chip ◽  
Many Core

Desempenho é um ponto crucial em arquiteturas many-core com networks-on-chip. Uma das alternativas para alcanç á-lo consiste em mapear processos nos núcleos de processamento de forma a minimizar o custo de comunicação global entre processos. Nesse contexto, esse trabalho propõe o algoritmo Kmeans como uma estratégia alternativa às heurísticas BRD e Guloso. Para determinados padrões de comunicação, os resultados de simulação apontaram que o Kmeans conduz a melhores mapeamentos que as outras estratégias, sendo portanto uma boa opção para o mapeamento de processos em arquiteturas many-core com networks-on-chip.

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