A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems

NORCHIP 2012 ◽  
2012 ◽  
Author(s):  
Haoyuan Ying ◽  
K. Heid ◽  
T. Hollstein ◽  
K. Hofmann
Keyword(s):  
Genetic Algorithm ◽  
Optimization Method ◽  
Networks On Chip ◽  
3 Dimensional ◽  
Link Density ◽  
On Chip ◽  
Many Core

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 ◽  
Author(s):  
Dexue Zhang ◽  
Xiaoyang Zeng ◽  
Zongyan Wang ◽  
Weike Wang ◽  
Xinhua Chen
Keyword(s):  
Networks On Chip ◽  
Virtual Platform ◽  
On Chip ◽  
Many Core

Software Defined Networks-on-Chip for Multi/Many-Core Systems

2016 ◽  
Author(s):  
R. Sandoval-Arechiga ◽  
R. Parra-Michel ◽  
J. L. Vazquez-Avila ◽  
J. Flores-Troncoso ◽  
S. Ibarra-Delgado
Keyword(s):  
Software Defined Networks ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

scholarly journals Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip

2018 ◽  
Vol 68 ◽  
pp. 581-602 ◽  
Author(s):  
Md Farhadur Reza ◽  
Dan Zhao ◽  
Hongyi Wu ◽  
Magdy Bayoumi
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
On Chip ◽  
Many Core

scholarly journals Algoritmo Kmeans para Mapeamento Estático de Processos em Redes-em-Chip

2014 ◽  
Author(s):  
Cíntia Avelar ◽  
Pedro Penna ◽  
Henrique Freitas
Keyword(s):  
Networks On Chip ◽  
On Chip ◽  
Many Core

Desempenho é um ponto crucial em arquiteturas many-core com networks-on-chip. Uma das alternativas para alcanç á-lo consiste em mapear processos nos núcleos de processamento de forma a minimizar o custo de comunicação global entre processos. Nesse contexto, esse trabalho propõe o algoritmo Kmeans como uma estratégia alternativa às heurísticas BRD e Guloso. Para determinados padrões de comunicação, os resultados de simulação apontaram que o Kmeans conduz a melhores mapeamentos que as outras estratégias, sendo portanto uma boa opção para o mapeamento de processos em arquiteturas many-core com networks-on-chip.

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