Comparative analysis of two gain- and offset-compensated very large time constant switched-capacitor integrators

Author(s):  
N.A. Radev ◽  
K.P. Ivanov
2019 ◽  
Vol 16 (3) ◽  
pp. 20181075-20181075
Author(s):  
Quan Li ◽  
Yan Li ◽  
Xiaosong Wang ◽  
Xin Liu ◽  
Yu Liu

2014 ◽  
Vol 53 (32) ◽  
pp. 7735 ◽  
Author(s):  
Xiao Lou ◽  
Lei Hou ◽  
Gaoyuan Guo ◽  
Wei Shi

2014 ◽  
Vol 23 (07) ◽  
pp. 1450093
Author(s):  
NGAI CHEONG

This paper describes an analysis of multi-stage and multi-rate IIR switched capacitor (SC) decimators using an interactive switched capacitor multi-rate compiler (ISCMRATE). Motivated by the experimental observations, the purpose of this paper is to explore a portion of characteristics for the multi-stage IIR SC decimators, with their implications in the context of a complete IIR SC filter. To overcome the limitations of conventional multi-stage IIR SC decimators, a novel solution has been introduced for the implementation of a multi-stage IIR SC circuit. Based on the statistical approach of the compiler, we provide the comparative analysis for different IIR SC decimators, including total capacitor area, capacitance spread and arbitrary anti-aliasing amplitude responses with a decimating factor in single and multi-stage building blocks. Examples are given to illustrate the practical feasibility of this compiler.


2013 ◽  
Vol 333-335 ◽  
pp. 22-26
Author(s):  
Xiao Fei Luo ◽  
Xian Xia ◽  
Kai Jun Wu

Aim at the electric power transformer with inductance is large, resistance is small, the inherent characteristics of the large time constant, a fast measurement scheme of power transformer winding DC resistance is proposed. The scheme adopts the increase the measurement circuit loop resistance mutation method, in which the circuit transition process from a time constant is forced to another time constant, to realize the rapid measurement of winding DC resistance in power transformer. Simulation results show the effectiveness of the scheme.


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