FPGA implementation of LDPC soft-decision decoders based DCSK for spread spectrum applications

<span lang="EN-US">Spread spectrum (SS) communications have attracted interest because of their channel attenuation immunity and low intercept potential. Apart from some extra features such as basic transceiver structures, chaotic communication would be the analog alternative to digital SS systems. Differential chaos shift keying (DCSK) systems, non-periodic and random characteristics among chaos carriers as well as their interaction with soft data are designed based on low-density parity-check (LDPC) codes in this brief. Because of simple structure, and glorious ability to <span>correct errors. Using the Xilinx kintex7 FPGA development kit, we investigate the hardware performance and resource requirement tendencies of the DCSK</span> communication system based on LDPC decoding algorithms (Prob. Domain, Log Domain and Min-Sum) over AWGN channel. The results indicate that the proposed system model has substantial improvements in the performance of the bit error rate (BER) and the real-time process. The Min-Sum decoder has relatively fewer FPGA resources than the other decoders. The implemented system will achieve 10-4 BER efficiency with 5 dB associate E_b/N_o as a coding gain.</span>

Creating Speech Synthesis Process by Using Pulse Model in Log-Domain Vocoder With Whale Optimized Deep Convolution Neural Networks

Speech synthesis is an artificial production of human speech by utilizing computer systems called a speech synthesizer. Several statistical parameters are used in previous works to perform the speech synthesis process, but the vocoder is combined only the simpler model. Due to the lack of sequence of modeling, the quality degrading process is reducing the speech synthesis. Therefore, the Pulse model in log-domain vocoder with whale optimized deep convolution recurrent neural network is applied to investing the vocoder in this work. During this analysis, Mel-Generalized Cepstrum (MGC), maximum voice frequency (MVF), and F0 are applied to processing the signal to extracting the features, and the vocoder is generated successfully. The system's effectiveness is then evaluated using experimental results compared to deep neural networks and traditional recurrent networks.

Noise analysis of translinear circuits

This thesis presents noise analysis of translinear circuits, or in general, log-domain filters. Due to the inherit companding [sic] behaviour and nonstationary nature of the translinear noise sources, a nonlinear noise analysis method is proposed.

Noise analysis of translinear circuits

This thesis presents noise analysis of translinear circuits, or in general, log-domain filters. Due to the inherit companding [sic] behaviour and nonstationary nature of the translinear noise sources, a nonlinear noise analysis method is proposed.

Design and implementation of log domain decoder

Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER.

Log-domain electronically-tuneable fully differential high order multi-function filter

This paper presents the synthesis of fully deferential circuit that is capable of performing simultaneous high-pass, low-pass, and band-pass filtering in the log domain. The circuit utilizes modified Seevinck’s integrators in the current mode. The transfer function describing the filter is first presented in the form of a canonical signal flow graph through applying Mason’s gain formula. The resulting signal flow graph consists of summing points and pick-off points associated with current mode integrators within unity-gain negative feedback loops. The summing points and the pick-off points are then synthesized as simple nodes and current mirrors, respectively. A new fully differential current-mode integrator circuit is proposed to realize the integration operation. The proposed integrator uses grounded capacitors with no resistors and can be adjusted to work as either lossless or lossy integrator via tuneable current sources. The gain and the cutoff frequency of the integrator are adjustable via biasing currents. Detailed design and simulation results of an example of a 5th order filter circuit is presented. The proposed circuit can perform simultaneously 5th order low-pass filtering, 5th order high-pass filtering, and 4th order band-pass filtering. The simulation is performed using Pspice with practical Infineon BFP649 BJT model. Simulation results show good matching with the target.