Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects

2017 ◽  
Author(s):  
Adrian Chasin ◽  
Erik Bury ◽  
Ben Kaczer ◽  
Jacopo Franco ◽  
Philippe Roussel ◽  
...  
Keyword(s):  
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Nanowire Transistors ◽  
Complete Degradation ◽  
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Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors

Nano Letters ◽  
2011 ◽  
Vol 11 (4) ◽  
pp. 1412-1417 ◽  
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Krutarth Trivedi ◽  
Hyungsang Yuk ◽  
Herman Carlo Floresca ◽  
Moon J. Kim ◽  
Walter Hu
Keyword(s):  
Quantum Confinement ◽  
Performance Enhancement ◽  
Si Nanowire ◽  
Nanowire Transistors

Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale

2018 ◽  
Author(s):  
S. Dey ◽  
T. P. Dash ◽  
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E. Mohapatra ◽  
J. Jena ◽  
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Keyword(s):  
Si Nanowire ◽  
Nanowire Transistors

Towards structured ASICs using polarity-tunable Si nanowire transistors

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Author(s):  
Pierre-Emmanuel Gaillardon ◽  
Michele De Marchi ◽  
Luca Amarù ◽  
Shashikanth Bobba ◽  
Davide Sacchetto ◽  
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Si Nanowire ◽  
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A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors

2010 ◽  
Vol 21 (43) ◽  
pp. 435201 ◽  
Author(s):  
Wei-Chen Chen ◽  
Horng-Chih Lin ◽  
Zer-Ming Lin ◽  
Chin-Tsai Hsu ◽  
Tiao-Yuan Huang
Keyword(s):  
Low Temperature ◽  
Transport Properties ◽  
Si Nanowire ◽  
Nanowire Transistors
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