Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors

Nano Letters ◽  
2011 ◽  
Vol 11 (4) ◽  
pp. 1412-1417 ◽  
Author(s):  
Krutarth Trivedi ◽  
Hyungsang Yuk ◽  
Herman Carlo Floresca ◽  
Moon J. Kim ◽  
Walter Hu
Keyword(s):  
Quantum Confinement ◽  
Performance Enhancement ◽  
Si Nanowire ◽  
Nanowire Transistors

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

2009 ◽  
Vol 30 (6) ◽  
pp. 644-646 ◽  
Author(s):  
Horng-Chih Lin ◽  
Wei-Chen Chen ◽  
Chuan-Ding Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Performance Enhancement ◽  
Si Nanowire ◽  
Nanowire Transistors ◽  
Channel Thickness

In Situ Doped Source/Drain for Performance Enhancement of Double-Gated Poly-Si Nanowire Transistors

2010 ◽  
Vol 57 (7) ◽  
pp. 1608-1615 ◽  
Author(s):  
Wei-Chen Chen ◽  
Horng-Chih Lin ◽  
Yu-Chia Chang ◽  
Chuan-Ding Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Performance Enhancement ◽  
Si Nanowire ◽  
Nanowire Transistors

Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale

2018 ◽  
Author(s):  
S. Dey ◽  
T. P. Dash ◽  
S. Das ◽  
E. Mohapatra ◽  
J. Jena ◽  
...  
Keyword(s):  
Si Nanowire ◽  
Nanowire Transistors
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