Parallel learning on the ArMenX machine by defining sub-networks

Author(s):  
Y. Autret ◽  
A. Thepaut ◽  
G. Ouvradou ◽  
J. Le Drezen ◽  
J.D. Laisne
Keyword(s):  
CENDEKIAWAN ◽  
2019 ◽  
Vol 1 (2) ◽  
pp. 10-15
Author(s):  
RIzka Harfiani ◽  
Hasrian Rudi Setiawan

Pendidikan inklusif kini menjadi fokus perhatian dalam upaya pemberian layanan pendidikan bagi semua anak, termasuk anak berkebutuhan khusus. Berbagai permasalahan kerap dijumpai dalam proses pembelajaran di kelas inklusif, untuk itu penelitian ini bertujuan menganalisis modifikasi alur pembelajaran harian pendidikan inklusif di Raudhatul Athfal An-Nahl, Jakarta. Penelitian ini menggunakan pendekatan kualitatif dengan jenis penelitian studi kasus. Teknik pengumpulan data yang digunakan adalah observasi, wawancara, dan dokumentasi. Teknis analisis data menggunakan model analisis interaktif Miles and Huberman, serta pengujian keabsahan data dengan metode triangulasi. Hasil penelitian menemukan modifikasi alur pembelajaran harian di RA. An-Nahl terdiri dari pre-opener, opener, energizer, activity, linking dan summeryzing, review, mission, dan closer. Hal yang perlu diperhatikan dalam proses pembelajaran adalah engagement, attention span, readiness, activity, reviewing, learning outcomes dan parallel learning outcomes. Kesimpulan dari penelitian ini menunjukkan bahwa modifikasi alur pembelajaran harian mampu mengakomodir kelebihan maupun kelemahan sesuai karakter masing-masing siswa, serta mampu mengatasi permasalahan dalam proses pembelajaran di kelas inklusif.


2021 ◽  
Vol 15 ◽  
Author(s):  
Wooseok Choi ◽  
Myonghoon Kwak ◽  
Seyoung Kim ◽  
Hyunsang Hwang

Hardware neural network (HNN) based on analog synapse array excels in accelerating parallel computations. To implement an energy-efficient HNN with high accuracy, high-precision synaptic devices and fully-parallel array operations are essential. However, existing resistive memory (RRAM) devices can represent only a finite number of conductance states. Recently, there have been attempts to compensate device nonidealities using multiple devices per weight. While there is a benefit, it is difficult to apply the existing parallel updating scheme to the synaptic units, which significantly increases updating process’s cost in terms of computation speed, energy, and complexity. Here, we propose an RRAM-based hybrid synaptic unit consisting of a “big” synapse and a “small” synapse, and a related training method. Unlike previous attempts, array-wise fully-parallel learning is possible with our proposed architecture with a simple array selection logic. To experimentally verify the hybrid synapse, we exploit Mo/TiOx RRAM, which shows promising synaptic properties and areal dependency of conductance precision. By realizing the intrinsic gain via proportionally scaled device area, we show that the big and small synapse can be implemented at the device-level without modifications to the operational scheme. Through neural network simulations, we confirm that RRAM-based hybrid synapse with the proposed learning method achieves maximum accuracy of 97 %, comparable to floating-point implementation (97.92%) of the software even with only 50 conductance states in each device. Our results promise training efficiency and inference accuracy by using existing RRAM devices.


2015 ◽  
Vol 27 (12) ◽  
pp. 3152-3165 ◽  
Author(s):  
Shuaiqiang Wang ◽  
Yun Wu ◽  
Byron J. Gao ◽  
Ke Wang ◽  
Hady W. Lauw ◽  
...  

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