Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog applications

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15nm gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡 ) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of (- 0.29) V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 109 , intrinsic gain (𝐴𝑉) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are offered for dielectric thickness of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of (-0.26 V), 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 1010 , (𝐴𝑉) of 175.69 dB and GFP of 2.39 GHz. For device reliability and stability study, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T). The results obtained are promising to meet the current display industry requirement. It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance.

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.

Design,Simulation And Analysis of Junction Version Multi-Fin FINFET

This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (µ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

Neural Network Training Acceleration With RRAM-Based Hybrid Synapses

Hardware neural network (HNN) based on analog synapse array excels in accelerating parallel computations. To implement an energy-efficient HNN with high accuracy, high-precision synaptic devices and fully-parallel array operations are essential. However, existing resistive memory (RRAM) devices can represent only a finite number of conductance states. Recently, there have been attempts to compensate device nonidealities using multiple devices per weight. While there is a benefit, it is difficult to apply the existing parallel updating scheme to the synaptic units, which significantly increases updating process’s cost in terms of computation speed, energy, and complexity. Here, we propose an RRAM-based hybrid synaptic unit consisting of a “big” synapse and a “small” synapse, and a related training method. Unlike previous attempts, array-wise fully-parallel learning is possible with our proposed architecture with a simple array selection logic. To experimentally verify the hybrid synapse, we exploit Mo/TiOx RRAM, which shows promising synaptic properties and areal dependency of conductance precision. By realizing the intrinsic gain via proportionally scaled device area, we show that the big and small synapse can be implemented at the device-level without modifications to the operational scheme. Through neural network simulations, we confirm that RRAM-based hybrid synapse with the proposed learning method achieves maximum accuracy of 97 %, comparable to floating-point implementation (97.92%) of the software even with only 50 conductance states in each device. Our results promise training efficiency and inference accuracy by using existing RRAM devices.

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N+ heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.

Comparative Analysis of Different Figures of Merit for Algan/Gan and Si Surrounding-Gate Field Effect Transistors (SG-Fets)

The combination of better transport properties of III-V group semiconductors along with excellent electrostatic control of surrounding gate is a promising option for the future low power electronics. Accordingly in this brief, the major figures of merit (FOM) including output current, output conductance (gd), transconductance generation factor (TGF), intrinsic gain (dB), and dynamic power dissipation are computed for surrounding-gate field effect transistors (SG-FETs) considering III-V group semiconductors and Si channel material respectively with respect to different device parameters. It is noticed that the center potential is higher in AlGaN/GaN SG-FET than Si for different values of channel length (CL), channel height (H), oxide thickness (tox), and doping concentration (Nd). The AlGaN/GaN SG-FET provides lower gd than Si for different values of CL, H, tox, and Nd as required for MOS analog circuits to achieve higher gain. The peak value of TGF and intrinsic gain is higher in AlGaN/GaN than Si SG-FET for different values of CL, H, tox, and Nd. In this work, we have analyzed the MOSFET structure for normally off operation of AlGaN/GaN high electron mobility transistors (HEMTs) to reduce dynamic power dissipation (PD). The magnitude of PD is calculated to be lower in normally off AlGaN/GaN SG-FET than Si for different values of CL, H, and tox.

Semiconductor-less vertical transistor with ION/IOFF of 106

Semiconductors have long been perceived as a prerequisite for solid-state transistors. Although switching principles for nanometer-scale devices have emerged based on the deployment of two-dimensional (2D) van der Waals heterostructures, tunneling and ballistic currents through short channels are difficult to control, and semiconducting channel materials remain indispensable for practical switching. In this study, we report a semiconductor-less solid-state electronic device that exhibits an industry-applicable switching of the ballistic current. This device modulates the field emission barrier height across the graphene-hexagonal boron nitride interface with ION/IOFF of 106 obtained from the transfer curves and adjustable intrinsic gain up to 4, and exhibits unprecedented current stability in temperature range of 15–400 K. The vertical device operation can be optimized with the capacitive coupling in the device geometry. The semiconductor-less switching resolves the long-standing issue of temperature-dependent device performance, thereby extending the potential of 2D van der Waals devices to applications in extreme environments.