An efficient modified probabilistic neural network hardware implementation for zero crossing thresholded binary signals

Author(s):  
A. Zaknich
2017 ◽  
Vol 25 (0) ◽  
pp. 42-48 ◽  
Author(s):  
Abul Hasnat ◽  
Anindya Ghosh ◽  
Amina Khatun ◽  
Santanu Halder

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.


2004 ◽  
Vol 8 (2) ◽  
pp. 208-213
Author(s):  
Noriyuki Aibe ◽  
Ryosuke Mizuno ◽  
Masanori Nakamura ◽  
Moritoshi Yasunaga ◽  
Ikuo Yoshihara

2004 ◽  
Vol 8 (2) ◽  
pp. 208-213 ◽  
Author(s):  
Noriyuki Aibe ◽  
Ryosuke Mizuno ◽  
Masanori Nakamura ◽  
Moritoshi Yasunaga ◽  
Ikuo Yoshihara

Author(s):  
Joel Minguet Lopez ◽  
Tifenn HIRTZLIN ◽  
Manon Dampfhoffer ◽  
Laurent Grenouillet ◽  
Lucas Reganaz ◽  
...  

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