scholarly journals Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

2017 ◽  
Vol 25 (0) ◽  
pp. 42-48 ◽  
Author(s):  
Abul Hasnat ◽  
Anindya Ghosh ◽  
Amina Khatun ◽  
Santanu Halder
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Probabilistic Neural Network ◽  
Clock Period ◽  
Data Set ◽  
Gate Arrays ◽  
Hardware System ◽  
Field Programmable ◽  
Programmable Gate Arrays

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

scholarly journals Implementation of Multispectral Image Classification on a Remote Adaptive Computer

VLSI Design ◽  
2000 ◽  
Vol 10 (3) ◽  
pp. 307-319
Author(s):  
Marco A. Figueiredo ◽  
Clay S. Gloster ◽  
Mark Stephens ◽  
Corey A. Graves ◽  
Mouna Nakkar
Keyword(s):  
Probabilistic Neural Network ◽  
General Purpose ◽  
Multispectral Images ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
General Purpose Computer ◽  
Server Application ◽  
Purpose Computer

As the demand for higher performance computers for the processing of remote sensing science algorithms increases, the need to investigate new computing paradigms is justified. Field Programmable Gate Arrays enable the implementation of algorithms at the hardware gate level, leading to orders of magnitude performance increase over microprocessor based systems. The automatic classification of spaceborne multispectral images is an example of a computation intensive application that can benefit from implementation on an FPGA-based custom computing machine (adaptive or reconfigurable computer). A probabilistic neural network is used here to classify pixels of a multispectral LANDSAT-2 image. The implementation described utilizes Java client/server application programs to access the adaptive computer from a remote site. Results verify that a remote hardware version of the algorithm (implemented on an adaptive computer) is significantly faster than a local software version of the same algorithm (implemented on a typical general-purpose computer).

HARDWARE IMPLEMENTATION OF A NEW ARTIFICIAL NEURON

2005 ◽  
Vol 15 (06) ◽  
pp. 427-433 ◽  
Author(s):  
RICHARD LABIB ◽  
FRANCIS AUDETTE ◽  
ALEXANDRE FORTIN ◽  
REZA ASSADI
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
External Temperature ◽  
Artificial Neuron ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
New Type ◽  
Software And Hardware

This paper describes an FPGA (Field Programmable Gate Arrays) implementation of a new type of neuron, the Quantron. The goal is to demonstrate the capability of current technology to closely recreate the human body's reaction to a change of temperature. This is accomplished by creating a function that adds a number of kernels at different frequencies depending on the external temperature. Once the sum of the kernels reaches a certain threshold, the artificial neural network, equivalent to its biological counterpart, "reacts" by sending a specific output signal designed to trigger a response. The various elements of each subsystem are discussed and implemented in software and hardware. The results are analyzed in terms of accuracy and efficiency compared to the biological equivalent.

A PROGRAMMABLE ACTIVE MEMORY IMPLEMENTATION OF A NEURAL NETWORK FOR SECOND LEVEL TRIGGERING IN ATLAS

1995 ◽  
Vol 06 (04) ◽  
pp. 561-566 ◽  
Author(s):  
LARS LUNDHEIM ◽  
IOSIF LEGRAND ◽  
LAURENT MOLL
Keyword(s):  
Regions Of Interest ◽  
Neural Net ◽  
Particle Type ◽  
Reconfigurable Processor ◽  
Gate Arrays ◽  
Active Memory ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Input Variables

In the second level triggering for ATLAS “Regions of Interest” (RoIs) are defined in (etha, phi) corresponding to possibly interesting particles. For each RoI physically meaningful parameters are extracted for each subdetector. Based on these parameters a classification of the particle type is made. A feed-forward neural net with 12 input variables, a 6-node intermediate layer, and 4 output nodes has earlier been suggested for this task. The reported work consists of an implementation of this neural net using a DECPeRLe-1, a Programmable Active Memory (PAM). This is a reconfigurable processor based on Field Programmable Gate Arrays (FPGAs), which has also been used for real-time implementation of feature extraction algorithms for second level triggering. The implementation is pipelined, runs with a clock of 25 MHz, and uses 0.64 microseconds for one particle classification. Integer arithmetic is used, and the performance is comparable to a floating point version.

scholarly journals Martian dust devils detector over FPGA

2011 ◽  
Vol 1 (1) ◽  
pp. 1-29
Author(s):  
E. de Lucas ◽  
M. J. Miguel ◽  
D. Mozos ◽  
L. Vázquez
Keyword(s):  
High Performance ◽  
Hardware Implementation ◽  
Small Volume ◽  
Space Missions ◽  
Reconfigurable Hardware ◽  
Dust Devil ◽  
Dust Devils ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Abstract. Digital applications that must be on-board of space missions must accomplish a very restrictive set of requirements. These include energy efficiency, small volume and weight, robustness and high performance. Moreover these circuits can not be repaired in case of error, so they must be reliable or provide some way to recover from errors. These features make reconfigurable hardware (FPGAs, Field Programmable Gate Arrays) a very suitable technology to be used in space missions. This paper presents a Martian dust devil detector implemented on a FPGA. The results show that a hardware implementation of the algorithm present very good numbers in terms of performance compared with the software version. Moreover, as the amount of time needed to perform all the computations on the reconfigurable hardware is small, this hardware can be used more of the time to realize other applications.

scholarly journals Designing and Implementing FPGA for AES

2019 ◽  
Vol 8 (11S) ◽  
pp. 953-955
Keyword(s):  
Hardware Implementation ◽  
Field Programmable Gate Arrays ◽  
Hardware Platform ◽  
Memory Space ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Method ◽  
Low Charge

The execution of DES and triple DES is not possible on hardware platform because they consume huge memory space. We can use field programmable gate arrays in order to do the hardware implementation because of its low charge, advertising space and reconfiguration nature. This paper aims at reducing the delay by using pipeline for speeding up the process. The proposed pipeline structure has a characteristic of having round keys which during iterations of encryption are utilized and an encryption method is used for generating them in parallel. The overall delay related to a delay of coding of plaintext block is reduced. The simulation is done in VHDL by Xilinx and implementation is done on FPGA Spartan 3E.

Engineering Technology and Accounting Science: Evolution and Futures Agenda

2021 ◽  
Vol 9 (3) ◽  
pp. 227-230
Keyword(s):  
Information Technology ◽  
Educational Institutions ◽  
Conceptual Approach ◽  
Engineering Technology ◽  
Gate Arrays ◽  
Hardware System ◽  
5G Network ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Function

This paper makes a novel inroad into engineering technology influence on modern accounting science and therefore provides awareness to accounting and finance professionals, the corporate and educational institutions on how engineering technology has become inextricably intertwined with the practice and learning of accounting. The paper thus aims to highlight how engineering technology has influenced and is rechanneling accounting mode of operations and function through the advancement in information technology apparatus. Using a conceptual approach, it shows how accounting has become synonymous with engineering technology and as such triggers the impetus for revamping accounting curriculum to accommodate the fundamental aspects of engineering study before concentrating on the core accounting modules. Accordingly, the paper makes initial recommendation for some information technology (IT)modules to form part of future accounting engineering curriculum. The IT modules that are proposed includes inter alia, cloud accounting, 5G Network and IOT Hardware System, Field-programmable gate arrays (FPGA), 3-D circuit architecture, Internet of Things and Industry 4.0, understanding and operation of Context-Aware Engine (CAE).

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