Reliability-driven high-level synthesis with clock frequency considered

2016 ◽  
Author(s):  
Wen-Zen Cheng ◽  
Chun-Hua Cheng ◽  
Shih-Hsu Huang
Keyword(s):  
High Level Synthesis ◽  
Clock Frequency ◽  
High Level

scholarly journals High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000

2021 ◽  
Vol 29 (2) ◽  
Author(s):  
Panadda Solod ◽  
Nattha Jindapetch ◽  
Kiattisak Sengchuai ◽  
Apidet Booranawong ◽  
Pakpoom Hoyingcharoen ◽  
...  
Keyword(s):  
Low Cost ◽  
Optimization Techniques ◽  
Lane Detection ◽  
High Level Synthesis ◽  
Resource Usage ◽  
Clock Frequency ◽  
Loop Analysis ◽  
Loop Unrolling ◽  
Loop Pipelining ◽  
High Level

In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA.

scholarly journals Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-18 ◽  
Author(s):  
Deepa Yagain ◽  
A. Vijaya Krishna
Keyword(s):  
Digital Filter ◽  
Computer Aided Design ◽  
Performance Metrics ◽  
Filter Design ◽  
Critical Path ◽  
Computation Time ◽  
Design Tool ◽  
High Level Synthesis ◽  
Clock Frequency ◽  
High Level

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

2014 ◽  
Vol E97.A (12) ◽  
pp. 2498-2506
Author(s):  
Akihiro SUDA ◽  
Hideki TAKASE ◽  
Kazuyoshi TAKAGI ◽  
Naofumi TAKAGI
Keyword(s):  
High Level Synthesis ◽  
Loop Parallelization ◽  
Polyhedral Optimization ◽  
High Level ◽  
Nested Loop

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level

Secure High-Level Synthesis: Challenges and Solutions

2021 ◽  
Author(s):  
Nitin Pundir ◽  
Farimah Farahmandi ◽  
Mark Tehranipoor
Keyword(s):  
High Level Synthesis ◽  
High Level
Sign in / Sign up

Export Citation Format

Share Document