Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip

19th IEEE International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2005.132 ◽

2005 ◽

Author(s):

H. Zimmer ◽

S. Zink ◽

T. Hollstein ◽

M. Glesner

Keyword(s):

Network On Chip ◽

Hierarchical Network ◽

Architecture Exploration ◽

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Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking

2006 15th Asian Test Symposium ◽

10.1109/ats.2006.260966 ◽

2006 ◽

Author(s):

Chunsheng Liu

Keyword(s):

Network On Chip ◽

Hierarchical Network ◽

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GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) ◽

10.1109/dsd.2007.4341514 ◽

2007 ◽

Author(s):

Christoph Puttmann ◽

Jorg-Christian Niemann ◽

Mario Porrmann ◽

Ulrich Ruckert

Keyword(s):

Chip Multiprocessors ◽

Network On Chip ◽

Hierarchical Network ◽

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Hierarchical Network-on-Chip for Embedded Many-Core Architectures

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip ◽

10.1109/nocs.2010.28 ◽

2010 ◽

Author(s):

Alexandre Guerre ◽

Nicolas Ventroux ◽

Raphaël David ◽

Alain Merigot

Keyword(s):

Network On Chip ◽

Hierarchical Network ◽

On Chip ◽

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A Fault Tolerant Hierarchical Network on Chip Router Architecture

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems ◽

10.1109/dft.2011.12 ◽

2011 ◽

Author(s):

M.H. Neishaburi ◽

Zeljko Zilic

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Hierarchical Network ◽

Router Architecture ◽

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Network-on-Chip Architecture Exploration Framework

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools ◽

10.1109/dsd.2009.192 ◽

2009 ◽

Author(s):

Timo Schonwald ◽

Jochen Zimmermann ◽

Oliver Bringmann ◽

Wolfgang Rosenstiel

Keyword(s):

Network On Chip ◽

Architecture Exploration ◽

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A Fault Tolerant Hierarchical Network on Chip Router Architecture

Journal of Electronic Testing ◽

10.1007/s10836-013-5398-4 ◽

2013 ◽

Vol 29 (4) ◽

pp. 485-497 ◽

Author(s):

M. H. Neishaburi ◽

Zeljko Zilic

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Hierarchical Network ◽

Router Architecture ◽

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A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2013.6673298 ◽

2013 ◽

Author(s):

Debora Matos ◽

Cezar Reinbrecht ◽

Tiago Motta ◽

Altamiro Susin

Keyword(s):

Network On Chip ◽

Hierarchical Network ◽

Power Efficient ◽

3D Ics ◽

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Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip ◽

10.1109/nocs.2012.17 ◽

2012 ◽

Author(s):

S. Carrillo ◽

J. Harkin ◽

L.J. McDaid ◽

S. Pande ◽

S. Cawley ◽

...

Keyword(s):

Neural Network ◽

Network On Chip ◽

Spiking Neural Network ◽

Hierarchical Network ◽

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Low Latency Mesh-based Hierarchical Network-on-Chip Structure

2015 The 5th International Workshop on Computer Science and Engineering-Information Processing and Control Engineering ◽

10.18178/wcse.2015.04.115 ◽

2015 ◽

Keyword(s):

Network On Chip ◽

Low Latency ◽

Hierarchical Network ◽

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Application driven network-on-chip architecture exploration & refinement for a complex SoC

Design Automation for Embedded Systems ◽

10.1007/s10617-011-9075-5 ◽

2011 ◽

Vol 15 (2) ◽

pp. 133-158 ◽

Author(s):

Jean-Jacques Lecler ◽

Gilles Baillieu

Keyword(s):

Network On Chip ◽

Architecture Exploration ◽

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