A Series Arc Fault Location Method for DC Distribution System Using Time Lag of Parallel Capacitor Current Pulses

Author(s):  
Xiaojun Liu
Energies ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 1983 ◽  
Author(s):  
Yan Xu ◽  
Jingyan Liu ◽  
Weijia Jin ◽  
Yuan Fu ◽  
Hui Yang

When a short circuit fault occurs on the DC side line, the fault current reaches the peak within a few milliseconds, and the voltage drops significantly. This phenomenon can cause overcurrent flowing through the DC line, semiconductor devices, and AC side, which is a major threat to the operation of the entire system. To solve this problem, this paper proposes a fault location scheme based on parameter identification. Firstly, the entire DC distribution system is regarded as a graph. The intersections of the distribution system lines are regarded as vertices. The current flow of each line is regarded as a directed edge. The network topology matrix is constructed and a fault type recognition algorithm is proposed based on graph theory. Secondly, the mathematical model of the pole-to-pole short-circuit fault and pole-to-ground short-circuit fault are analyzed with double-ended electrical quantities. Transform the fault location problem into a parameter identification problem, four parameters to be identified are extracted, and the fitness function is constructed separately for two kinds of fault cases. Thirdly, a genetic algorithm (GA) is adopted to identify the value of parameters. Considering the fault types, transition resistance and fault location, the Matlab/Simulink simulation platform is used to simulate 18 fault conditions. The simulation results show that the positioning error of the fault location method is less than 1%, which is not affected by the transition resistance and has strong robustness.


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