Low power scheduling method using multiple supply voltages

2006 ◽  
Author(s):  
Kun-Lin Tsai ◽  
Ju-Yueh Lee ◽  
Shanq-Jang Ruan ◽  
Feipei Lai
Keyword(s):  
Low Power ◽  
Power Scheduling ◽  
Scheduling Method ◽  
Supply Voltages ◽  
Multiple Supply Voltages

Automated low-power technique exploiting multiple supply voltages applied to a media processor

1998 ◽  
Vol 33 (3) ◽  
pp. 463-472 ◽  
Author(s):  
K. Usami ◽  
M. Igarashi ◽  
F. Minami ◽  
T. Ishikawa ◽  
M. Kanzawa ◽  
...  
Keyword(s):  
Low Power ◽  
Media Processor ◽  
Supply Voltages ◽  
Multiple Supply Voltages

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

2006 ◽  
Vol 35 (1) ◽  
pp. 93-113
Author(s):  
Ling Wang ◽  
Yingtao Jiang ◽  
Henry Selvaraj
Keyword(s):  
Low Power ◽  
Supply Voltages ◽  
Multiple Supply Voltages

scholarly journals AN OPTIMIZATION-BASED MULTIPLE-VOLTAGE SCALING TECHNIQUE FOR LOW-POWER CMOS DIGITAL DESIGN

2002 ◽  
Vol 11 (04) ◽  
pp. 365-375 ◽  
Author(s):  
YI-JONG YEH ◽  
SY-YEN KUO
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Path Selection ◽  
Digital Design ◽  
Selection Algorithm ◽  
Scaling Technique ◽  
Low Power Cmos ◽  
Optimal Values ◽  
Supply Voltages ◽  
Multiple Supply Voltages

In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.

scholarly journals Low Power Bidirectional Voltage Level Translator using Power Gating

2020 ◽  
Vol 9 (7) ◽  
pp. 977-981
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Gating ◽  
Voltage Level ◽  
Supply Voltages ◽  
Reduced Power Consumption ◽  
Multiple Supply Voltages

now a day’s, the demand for SoC based systems increasing. In SoC environment, multiple supply voltages are required because various subsystems of the system operate with different supply voltages. The communication between these systems is difficult and increases power consumption. The solution to this problem is to use a Voltage level translator/shifter between them. In this paper, a low power voltage level translator using power gating is proposed. By using this translator bidirectional voltage translator is implemented. In bidirectional voltage level translator, the data is translation between core logic and pad drivers and vice versa is possible with reduced power consumption and delay. In this paper, the power consumption reduces from 104uw to 6.25 pw at Vdd 1.8V. Delay is reduced from 19ns to 0.2 ns.

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