An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme

2018 ◽  
Author(s):  
Ming-Yan Tsai ◽  
Po-Yu Kuo ◽  
Jin-Fa Lin ◽  
Ming-Hwa Sheu
Keyword(s):  
Low Power ◽  
Time Variation ◽  
Single Phase ◽  
Hold Time ◽  
Reduction Scheme ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Logic Structure

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

2017 ◽  
Vol 25 (11) ◽  
pp. 3033-3044 ◽  
Author(s):  
Jin-Fa Lin ◽  
Ming-Hwa Sheu ◽  
Yin-Tsung Hwang ◽  
Chen-Syuan Wong ◽  
Ming-Yan Tsai
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Logic Structure

Ultra-low power subthreshold flip-flop design

2009 ◽  
Author(s):  
Sagi Fisher ◽  
Adam Teman ◽  
Dmitry Vaysman ◽  
Alexander Gertsman ◽  
Orly Yadid-Pecht ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 756-761
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

2014 ◽  
Vol 61 (6) ◽  
pp. 1755-1765 ◽  
Author(s):  
Djaafar Chabi ◽  
Weisheng Zhao ◽  
Erya Deng ◽  
Yue Zhang ◽  
Nesrine Ben Romdhane ◽  
...  
Keyword(s):  
Low Power ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

2010 ◽  
Vol 57 (1) ◽  
pp. 72-82 ◽  
Author(s):  
M.V. Krishna ◽  
Manh Anh Do ◽  
Kiat Seng Yeo ◽  
Chirn Chye Boon ◽  
Wei Meng Lim
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Ultra Low Power ◽  
Phase Clock
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