Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

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An Ultra-Low-Power Pulse Oximeter Implemented With an Energy-Efficient Transimpedance Amplifier

IEEE Transactions on Biomedical Circuits and Systems ◽

10.1109/tbcas.2009.2033035 ◽

2010 ◽

Vol 4 (1) ◽

pp. 27-38 ◽

Cited By ~ 91

Author(s):

Maziar Tavakoli ◽

Lorenzo Turicchia ◽

Rahul Sarpeshkar

Keyword(s):

Low Power ◽

Pulse Oximeter ◽

Energy Efficient ◽

Transimpedance Amplifier ◽

Ultra Low Power ◽

Power Pulse

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Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2013.2295026 ◽

2014 ◽

Vol 61 (6) ◽

pp. 1755-1765 ◽

Cited By ~ 56

Author(s):

Djaafar Chabi ◽

Weisheng Zhao ◽

Erya Deng ◽

Yue Zhang ◽

Nesrine Ben Romdhane ◽

...

Keyword(s):

Low Power ◽

Power Gating ◽

Flip Flop ◽

Ultra Low Power

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Ultra-low power NAND based multiplexer and flip-flop

2013 Nirma University International Conference on Engineering (NUiCONE) ◽

10.1109/nuicone.2013.6780110 ◽

2013 ◽

Author(s):

Ishan Varun ◽

Tarun Kumar Gupta

Keyword(s):

Low Power ◽

Flip Flop ◽

Ultra Low Power

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250-MHz resonator based energy recovery flip-flop for ultra low-power clocking

2015 Global Conference on Communication Technologies (GCCT) ◽

10.1109/gcct.2015.7342683 ◽

2015 ◽

Author(s):

Debidutta Nanda ◽

Rajendra Prasad

Keyword(s):

Low Power ◽

Energy Recovery ◽

Flip Flop ◽

Ultra Low Power

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Subthreshold Region based Linear Feedback Shift Register

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.f1205.0886s219 ◽

2019 ◽

Vol 8 (6S2) ◽

pp. 817-821

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

High Speed ◽

System Level ◽

Linear Feedback ◽

Portable Devices ◽

Subthreshold Region ◽

Flip Flop ◽

Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

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