Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

2014 ◽  
Vol 61 (6) ◽  
pp. 1755-1765 ◽  
Author(s):  
Djaafar Chabi ◽  
Weisheng Zhao ◽  
Erya Deng ◽  
Yue Zhang ◽  
Nesrine Ben Romdhane ◽  
...  
Keyword(s):  
Low Power ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Design and Analysis of Low Power Dual Edge Triggered Mechanism Flip-Flop Employing Power Gating Methodology

2020 ◽  
Vol 6 (01) ◽  
pp. 26-31
Author(s):  
Prof. Virendra Umale
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Reduction Technique ◽  
Power Gating ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Efficient Power

The advancement of battery operated designs has abundantly increases the memory elements and registers to be operated in ultra-low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique.  The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the ground terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design.

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power

Ultra-low power subthreshold flip-flop design

2009 ◽  
Author(s):  
Sagi Fisher ◽  
Adam Teman ◽  
Dmitry Vaysman ◽  
Alexander Gertsman ◽  
Orly Yadid-Pecht ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power

New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems

2011 ◽  
Vol 10 (11) ◽  
pp. 2161-2167 ◽  
Author(s):  
Jianping Hu ◽  
Xiaoying Yu ◽  
Jindan Chen
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Power Gating ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Gating Scheme

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 756-761
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse

A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Integration ◽  
2018 ◽  
Vol 60 ◽  
pp. 160-166 ◽  
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Leakage Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse ◽  
Novel Design
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