Irregularly shaped voltage islands generation with hazard and heal strategy

2010 ◽

Cited By ~ 1

Author(s):

Asit K. Mishra ◽

Shekhar Srikantaiah ◽

Mahmut Kandemir ◽

Chita R. Das

Keyword(s):

Power Management ◽

Voltage Islands

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Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2012.2203600 ◽

2012 ◽

Vol 31 (11) ◽

pp. 1754-1766 ◽

Cited By ~ 22

Author(s):

X. Kavousianos ◽

K. Chakrabarty ◽

A. Jain ◽

R. Parekhji

Keyword(s):

Voltage Scaling ◽

Dynamic Voltage Scaling ◽

Schedule Optimization ◽

Dynamic Voltage ◽

Test Schedule ◽

Voltage Islands

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Low power design with multi-Vdd and voltage islands (Abstract)

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415881 ◽

2007 ◽

Cited By ~ 4

Author(s):

Martin D. F. Wong

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Islands

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Energy Efficient Real Time Scheduling on Multi-core Processor with Voltage Islands

2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) ◽

10.1109/icacci.2018.8554680 ◽

2018 ◽

Cited By ~ 1

Author(s):

Mayuri Digalwar ◽

Praveen Gahukar ◽

Sudeept Mohan

Keyword(s):

Real Time ◽

Energy Efficient ◽

Real Time Scheduling ◽

Time Scheduling ◽

Multi Core Processor ◽

Voltage Islands

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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Integration ◽

10.1016/j.vlsi.2011.11.010 ◽

2012 ◽

Vol 45 (3) ◽

pp. 271-281 ◽

Cited By ~ 7

Author(s):

Nishit Kapadia ◽

Sudeep Pasricha

Keyword(s):

Low Power ◽

Interconnection Networks ◽

Networks On Chip ◽

On Chip ◽

Low Power Synthesis ◽

Voltage Islands

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Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) ◽

10.1109/ets.2012.6233019 ◽

2012 ◽

Cited By ~ 6

Author(s):

Xrysovalantis Kavousianos ◽

Krishnendu Chakrabarty ◽

Arvind Jain ◽

Rubin Parekhji

Keyword(s):

Time Division Multiplexing ◽

Time Division ◽

Voltage Islands

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A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_27 ◽

2005 ◽

pp. 257-266 ◽

Cited By ~ 7

Author(s):

Yici Cai ◽

Bin Liu ◽

Qiang Zhou ◽

Xianlong Hong

Keyword(s):

Low Power ◽

Voltage Islands

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NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09 ◽

10.1145/1629911.1630121 ◽

2009 ◽

Cited By ~ 16

Author(s):

Ciprian Seiculescu ◽

Srinivasan Murali ◽

Luca Benini ◽

Giovanni De Micheli

Keyword(s):

Voltage Islands

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Session 4A - Buffers and voltage islands

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. ◽

10.1109/iccad.2005.1560084 ◽

2005 ◽

Keyword(s):

Voltage Islands

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Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

Architecture of Computing Systems – ARCS 2012 - Lecture Notes in Computer Science ◽

10.1007/978-3-642-28293-5_5 ◽

2012 ◽

pp. 50-62 ◽

Cited By ~ 12

Author(s):

Nikita Nikitin ◽

Jordi Cortadella

Keyword(s):

Chip Multiprocessors ◽

Task Mapping ◽

Voltage Islands

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Irregularly shaped voltage islands generation with hazard and heal strategy

Coordinated power management of voltage islands in CMPs

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

Low power design with multi-Vdd and voltage islands (Abstract)

Energy Efficient Real Time Scheduling on Multi-core Processor with Voltage Islands

A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design

NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Session 4A - Buffers and voltage islands

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

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