Low power synthesis for asynchronous FIFO using unified power format (UPF)

Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

IoT based reconfigurable smart city architecture

Now-a-days Internet of Things is deployed almost in every application regarding smart cities and have been initiated to develop all over the world. Smart Devices are being geared up to ease human life. Due to the growth in Internet of Things technology, smart cities are been developedwith this technology to work with the issues of public as well as private. The aim of the article is to enhance a solution to the problems in the smart cities with latest IoT architecture, protocols and services. With the technical support of IoT, using low power Wireless Sensor Networks (WSN) which is connected to transfer the data from M2M applications. In addition to the IoT, intelligent features are integrated with the help of Computer vision makes the technology more flexible. The goal of this article is to engrave the services to challenge the real time environment with low power synthesis technique. Only then, the smart city features are improved and serves the mankind with IoT technology.

Low Power Synthesis of Finite State Machines — State Assignment Decomposition Algorithm

A new method for reducing power consumption in finite state machines (FSMs) is proposed. Probabilistic description of the FSMs is the theoretical background of power-oriented state assignment. The algorithm of state assignment is based on a decomposition strategy of coding. This idea uses a binary tree in which nodes are created by sharing a finite state machine. The algorithm has been applied to the LGSynth91 benchmark and has also been compared to other approaches. The experiments showed that the proposed method leads to a reduction in power consumption compared to the state encoding algorithms that have already been developed. Reduction of the circuits’ area is also observed.