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Clock tree optimization through selective airgap insertion
2017 18th International Symposium on Quality Electronic Design (ISQED)
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10.1109/isqed.2017.7918317
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2017
◽
Author(s):
Daijoon Hyun
◽
Wachirawit Ponghiran
◽
Youngsoo Shin
Keyword(s):
Clock Tree
◽
Tree Optimization
Download Full-text
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References
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration
◽
10.1016/j.vlsi.2012.04.004
◽
2013
◽
Vol 46
(1)
◽
pp. 22-32
◽
Cited By ~ 5
Author(s):
Sina Basir-Kazeruni
◽
Hao Yu
◽
Fang Gong
◽
Yu Hu
◽
Chunchen Liu
◽
...
Keyword(s):
Stochastic Perturbation
◽
Clock Tree
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Tree Optimization
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Clock Tree Optimization of FPGA Semi-Custom Memory with SEU FlipFlops
2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS)
◽
10.1109/iemtronics51293.2020.9216346
◽
2020
◽
Author(s):
Sourabh Aditya Swarnkar
◽
Kumar Rahul
◽
Mohammad Anees
◽
Santosh Yachareni
Keyword(s):
Clock Tree
◽
Tree Optimization
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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
◽
10.1145/513918.514021
◽
2002
◽
Cited By ~ 2
Author(s):
Mustafa Badaroglu
◽
Kris Tiri
◽
StÉphane Donnay
◽
Piet Wambacq
◽
Hugo De Man
◽
...
Keyword(s):
Noise Reduction
◽
Digital Circuits
◽
Substrate Noise
◽
Clock Tree
◽
Tree Optimization
◽
Supply Current
◽
Current Transients
Download Full-text
OCV-aware top-level clock tree optimization
Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14
◽
10.1145/2591513.2591541
◽
2014
◽
Cited By ~ 10
Author(s):
Tuck-Boon Chan
◽
Kwangsoo Han
◽
Andrew B. Khang
◽
Jae-Gon Lee
◽
Siddhartha Nath
Keyword(s):
Clock Tree
◽
Tree Optimization
Download Full-text
Taco: temperature aware clock-tree optimization
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.
◽
10.1109/iccad.2005.1560133
◽
2005
◽
Cited By ~ 39
Author(s):
M. Cho
◽
S. Ahmed
◽
D.Z. Pan
Keyword(s):
Clock Tree
◽
Tree Optimization
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Low-power gated clock tree optimization for three-dimensional integrated circuits
VLSI Design, Automation and Test(VLSI-DAT)
◽
10.1109/vlsi-dat.2015.7114530
◽
2015
◽
Cited By ~ 1
Author(s):
Yu-Chuan Chen
◽
Chih-Cheng Hsu
◽
Mark Po-Hung Lin
Keyword(s):
Integrated Circuits
◽
Low Power
◽
Three Dimensional
◽
Clock Tree
◽
Tree Optimization
◽
Gated Clock
Download Full-text
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/2491477.2491484
◽
2013
◽
Vol 18
(3)
◽
pp. 1-20
◽
Cited By ~ 10
Author(s):
Sean Shih-Ying Liu
◽
Wan-Ting Lo
◽
Chieh-Jui Lee
◽
Hung-Ming Chen
Keyword(s):
Clock Tree
◽
Flip Flop
◽
Tree Optimization
Download Full-text
Low Power Clock Tree Optimization by Clock Buffer/Inverter Reduction
2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
◽
10.1109/icta48799.2019.9012842
◽
2019
◽
Author(s):
Zhe Ge
◽
Juan Fu
◽
Peidong Wang
Keyword(s):
Low Power
◽
Clock Tree
◽
Tree Optimization
Download Full-text
MCMM clock tree optimization based on slack redistribution using a reduced slack graph
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
◽
10.1109/aspdac.2016.7428039
◽
2016
◽
Cited By ~ 5
Author(s):
Rickard Ewetz
◽
Cheng-Kok Koh
Keyword(s):
Clock Tree
◽
Tree Optimization
Download Full-text
A Clock Tree Optimization Framework with Predictable Timing Quality
Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17
◽
10.1145/3061639.3062184
◽
2017
◽
Cited By ~ 2
Author(s):
Rickard Ewetz
Keyword(s):
Clock Tree
◽
Optimization Framework
◽
Tree Optimization
Download Full-text
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