A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

2002 ◽  
Author(s):  
K. Ueda ◽  
K. Nii ◽  
Y. Wada ◽  
I. Takimoto ◽  
S. Maeda ◽  
...  
Keyword(s):  
Gate Array ◽  
Soi Cmos

A 0.35 μm 560 KG SOI/CMOS gate array using field-shield isolation technique

2002 ◽  
Author(s):  
K. Mashiko ◽  
K. Ueda ◽  
K. Nii ◽  
Y. Wada ◽  
T. Hirota ◽  
...  
Keyword(s):  
Isolation Technique ◽  
Gate Array ◽  
Soi Cmos

SOI / CMOS Gate Array by Laser Recrystallization

1984 ◽  
Author(s):  
Tetsuo Izawa ◽  
Seiichiro Kawamura ◽  
Nobuo Sasaki ◽  
Motoo Nakano ◽  
Kunihiko Wada ◽  
...  
Keyword(s):  
Laser Recrystallization ◽  
Gate Array ◽  
Soi Cmos

Heat Diffusion in an Optical Logic Gate Array on Silicon-on-Sapphire

1997 ◽  
Vol 7 (3) ◽  
pp. 739-748
Author(s):  
H. Gualous ◽  
A. Koster ◽  
D. Pascal ◽  
S. Laval
Keyword(s):  
Logic Gate ◽  
Heat Diffusion ◽  
Optical Logic ◽  
Optical Logic Gate ◽  
Gate Array

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications

2016 ◽  
Vol E99.C (6) ◽  
pp. 717-726
Author(s):  
Nobutaro SHIBATA ◽  
Yoshinori GOTOH ◽  
Takako ISHIHARA
Keyword(s):  
High Density ◽  
Gate Array

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array
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